diff options
| -rw-r--r-- | kernel/rtlil.h | 4 | ||||
| -rw-r--r-- | passes/equiv/equiv_make.cc | 28 |
2 files changed, 21 insertions, 11 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 276540aa1..3323f13f0 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1304,6 +1304,10 @@ inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const { } inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { + if(sig.size() != 1 || sig.chunks().size() != 1) { + std::cout << "rtp " << sig.size() << std::endl; + std::cout << "rtp " << sig.chunks().size() << std::endl; + } log_assert(sig.size() == 1 && sig.chunks().size() == 1); *this = SigBit(sig.chunks().front()); } diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 66ee28aff..8489abe7c 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -290,22 +290,28 @@ struct EquivMakeWorker init_bit2driven(); - pool<Cell*> visited_cells; + pool<Cell*> visited_cells; for (auto c : cells_list) for (auto &conn : c->connections()) if (!ct.cell_output(c->type, conn.first)) { SigSpec old_sig = assign_map(conn.second); SigSpec new_sig = rd_signal_map(old_sig); - - visited_cells.clear(); - if (old_sig != new_sig) { - if (check_signal_in_fanout(visited_cells, old_sig, new_sig)) - continue; - log("Changing input %s of cell %s (%s): %s -> %s\n", - log_id(conn.first), log_id(c), log_id(c->type), - log_signal(old_sig), log_signal(new_sig)); - c->setPort(conn.first, new_sig); + if(old_sig != new_sig) { + for(auto & old_bit : old_sig.bits()) { + SigBit new_bit = new_sig.bits()[old_bit.offset]; + + visited_cells.clear(); + if (old_bit != new_bit) { + if (check_signal_in_fanout(visited_cells, old_bit, new_bit)) + continue; + + log("Changing input %s of cell %s (%s): %s -> %s\n", + log_id(conn.first), log_id(c), log_id(c->type), + log_signal(old_bit), log_signal(new_bit)); + c->setPort(conn.first, new_bit); + } + } } } @@ -412,7 +418,7 @@ struct EquivMakeWorker } } - bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit) + bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigSpec source_bit, SigSpec target_bit) { if (source_bit == target_bit) return true; |