diff options
| -rw-r--r-- | tests/arch/ecp5/latches_abc9.ys | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys new file mode 100644 index 000000000..ca3182254 --- /dev/null +++ b/tests/arch/ecp5/latches_abc9.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module top(input e, d, output q); +reg l; +always @* + if (e) + l = ~d; +assign q = ~l; +endmodule +EOT +proc +design -save gold + +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ecp5 -abc9 +select -assert-count 2 t:LUT4 +select -assert-none t:LUT4 %% t:* %D |