diff options
| -rw-r--r-- | backends/aiger/xaiger.cc | 6 | ||||
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 9 | ||||
| -rw-r--r-- | passes/techmap/abc9.cc | 12 |
3 files changed, 15 insertions, 12 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 582e8e076..3c96f6c9e 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -879,13 +879,15 @@ struct XAigerWriter int i = std::get<3>(c); int a = bit2aig(b); log_assert((a & 1) == 0); - input_lines[a] += stringf("cinput %d %d %s %s\n", (a >> 1)-1, i, log_id(std::get<1>(c)), log_id(std::get<2>(c))); + RTLIL::Cell* cell = std::get<1>(c); + input_lines[a] += stringf("cinput %d %d %s %s %s\n", (a >> 1)-1, i, log_id(cell), log_id(std::get<2>(c)), log_id(cell->type)); } for (const auto &c : co_bits) { int i = std::get<3>(c); int o = std::get<4>(c); - output_lines[o] += stringf("coutput %d %d %s %s\n", o, i, log_id(std::get<1>(c)), log_id(std::get<2>(c))); + RTLIL::Cell* cell = std::get<1>(c); + output_lines[o] += stringf("coutput %d %d %s %s %s\n", o, i, log_id(cell), log_id(std::get<2>(c)), log_id(cell->type)); } input_lines.sort(); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 2441ee937..6c174871b 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -720,14 +720,17 @@ void AigerReader::post_process() } else log_abort(); - std::string port; - mf >> port; + std::string port, type; + mf >> port >> type; RTLIL::IdString cell_name = RTLIL::escape_id(symbol); RTLIL::IdString cell_port = RTLIL::escape_id(port); + RTLIL::IdString cell_type = RTLIL::escape_id(type); RTLIL::Cell* cell = module->cell(cell_name); if (!cell) - cell = module->addCell(cell_name, "$__blackbox__"); + cell = module->addCell(cell_name, cell_type); + else + log_assert(cell->type == cell_type); wire->port_input = false; wire->port_output = false; if (cell->hasPort(cell_port)) { diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 89e3eb948..475508e02 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -535,18 +535,18 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_error("Can't open ABC output file `%s'.\n", buffer.c_str()); bool builtin_lib = liberty_file.empty(); - RTLIL::Design *mapped_design = new RTLIL::Design; //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode); buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym"); - AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */); + log_assert(!design->module("$__abc9__")); + AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */); reader.parse_xaiger(); ifs.close(); log_header(design, "Re-integrating ABC9 results.\n"); - RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"]; + RTLIL::Module *mapped_mod = design->module("$__abc9__"); if (mapped_mod == NULL) - log_error("ABC output file does not contain a module `netlist'.\n"); + log_error("ABC output file does not contain a module `$__abc9__'.\n"); pool<RTLIL::SigBit> output_bits; for (auto &it : mapped_mod->wires_) { @@ -801,7 +801,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri else { cell = module->cell(c->name); log_assert(cell); - log_assert(c->type == "$__blackbox__"); + log_assert(c->type == cell->type); } if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; @@ -937,8 +937,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires); log("ABC RESULTS: input signals: %8d\n", in_wires); log("ABC RESULTS: output signals: %8d\n", out_wires); - - delete mapped_design; } //else //{ |