diff options
| -rw-r--r-- | kernel/rtlil.cc | 1 | ||||
| -rw-r--r-- | passes/memory/memory_bram.cc | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ad90965fb..72809d42d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1482,6 +1482,7 @@ void RTLIL::Module::connect(const RTLIL::SigSig &conn) log_backtrace("-X- ", yosys_xtrace-1); } + log_assert(GetSize(conn.first) == GetSize(conn.second)); connections_.push_back(conn); } diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 7b5dd08ab..a7f9cf382 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -656,6 +656,9 @@ grow_read_ports:; bool transp = rd_transp[cell_port_i] == State::S1; SigBit clksig = rd_clk[cell_port_i]; + if (wr_ports == 0) + transp = false; + pair<SigBit, bool> clkdom(clksig, clkpol); if (!clken) clkdom = pair<SigBit, bool>(State::S1, false); |