diff options
| -rw-r--r-- | CHANGELOG | 15 | ||||
| -rw-r--r-- | Makefile | 4 |
2 files changed, 16 insertions, 3 deletions
@@ -2,11 +2,24 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.23 .. Yosys 0.23-dev +Yosys 0.23 .. Yosys 0.24 -------------------------- + * New commands and options + - Added option "-set-def-formal" to "sat" pass. + - Added option "-s" to "tee" command. * Verilog - Support for module-scoped identifiers referring to tasks and functions. + - Support for arrays with swapped ranges within structs. + + * Verific support + - Support for importing verilog configurations per name. + - "verific -set-XXXXX" commands are now able to set severity to all messages + of certain type (errors, warnings, infos and comments) + + * Various + - TCL shell support (use "yosys -C") + - Added FABulous eFPGA frontend Yosys 0.22 .. Yosys 0.23 -------------------------- @@ -142,7 +142,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.23+45 +YOSYS_VER := 0.24 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -158,7 +158,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 7ce5011.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 7ce5011.. | wc -l`/;" Makefile # set 'ABCREV = default' to use abc/ as it is # |