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| -rw-r--r-- | CHANGELOG | 21 | ||||
| -rw-r--r-- | CODEOWNERS | 1 |
2 files changed, 22 insertions, 0 deletions
@@ -5,6 +5,27 @@ List of major changes and improvements between releases Yosys 0.11 .. Yosys 0.11-dev -------------------------- + * Various + - Added iopadmap native support for negative-polarity output enable + - ABC update + + * SystemVerilog + - Support parameters using struct as a wiretype + + * New commands and options + - Added "-genlib" option to "abc" pass + - Added "sta" very crude static timing analysis pass + + * Verific support + - Fixed memory block size in import + + * New back-ends + - Added support for GateMate FPGA from Cologne Chip AG + + * Intel ALM support + - Added preliminary Arria V support + + Yosys 0.10 .. Yosys 0.11 -------------------------- diff --git a/CODEOWNERS b/CODEOWNERS index 26d838bec..19b660dff 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -32,6 +32,7 @@ frontends/ast/ @zachjs techlibs/intel_alm/ @ZirconiumX techlibs/gowin/ @pepijndevos +techlibs/gatemate/ @pu-cc # pyosys misc/*.py @btut |