diff options
| -rw-r--r-- | passes/cmds/chformal.cc | 8 | ||||
| -rw-r--r-- | tests/various/chformal_coverenable.ys (renamed from tests/various/chformal_coverprecond.ys) | 6 |
2 files changed, 7 insertions, 7 deletions
diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index c4666f1f0..c3590855b 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -55,8 +55,8 @@ struct ChformalPass : public Pass { log(" -skip <N>\n"); log(" ignore activation of the constraint in the first <N> clock cycles\n"); log("\n"); - log(" -coverprecond\n"); - log(" add a cover statement for the precondition (enable signal) of the cells\n"); + log(" -coverenable\n"); + log(" add cover statements for the enable signals of the constraints\n"); log("\n"); log(" -assert2assume\n"); log(" -assume2assert\n"); @@ -117,7 +117,7 @@ struct ChformalPass : public Pass { mode_arg = atoi(args[++argidx].c_str()); continue; } - if (mode == 0 && args[argidx] == "-coverprecond") { + if (mode == 0 && args[argidx] == "-coverenable") { mode = 'p'; continue; } @@ -273,7 +273,7 @@ struct ChformalPass : public Pass { if (mode =='p') { for (auto cell : constr_cells) - module->addCover(NEW_ID_SUFFIX("coverprecond"), + module->addCover(NEW_ID_SUFFIX("coverenable"), cell->getPort(ID::EN), State::S1, cell->get_src_attribute()); } else diff --git a/tests/various/chformal_coverprecond.ys b/tests/various/chformal_coverenable.ys index 59e302a72..52b3ee6bf 100644 --- a/tests/various/chformal_coverprecond.ys +++ b/tests/various/chformal_coverenable.ys @@ -15,11 +15,11 @@ prep -top top select -assert-count 1 t:$cover -chformal -cover -coverprecond +chformal -cover -coverenable select -assert-count 2 t:$cover -chformal -assert -coverprecond +chformal -assert -coverenable select -assert-count 4 t:$cover -chformal -assume -coverprecond +chformal -assume -coverenable select -assert-count 5 t:$cover |