diff options
| -rw-r--r-- | passes/techmap/Makefile.inc | 1 | ||||
| -rw-r--r-- | passes/techmap/clkpart.cc | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index cd357d72a..13992315e 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -41,6 +41,7 @@ OBJS += passes/techmap/zinit.o OBJS += passes/techmap/dff2dffs.o OBJS += passes/techmap/flowmap.o OBJS += passes/techmap/extractinv.o +OBJS += passes/techmap/clkpart.o endif GENFILES += passes/techmap/techmap.inc diff --git a/passes/techmap/clkpart.cc b/passes/techmap/clkpart.cc index 4fa729250..bf3b5bd30 100644 --- a/passes/techmap/clkpart.cc +++ b/passes/techmap/clkpart.cc @@ -144,7 +144,7 @@ struct ClkPartPass : public Pass { { bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_)); bool this_en_pol = !enable_mode || cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)); - key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E)) : RTLIL::SigSpec())); + key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E))) : RTLIL::SigSpec()); } else continue; |