diff options
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 534cc0daa..ac9e31f70 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -901,11 +901,6 @@ void AigerReader::post_process() RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable)); if (cell) { // ABC could have optimised this box away module->rename(cell, escaped_s); - #ifndef NDEBUG - RTLIL::Module* box_module = design->module(cell->type); - log_assert(box_module); - #endif - for (const auto &i : cell->connections()) { RTLIL::IdString port_name = i.first; RTLIL::SigSpec rhs = i.second; |