aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--techlibs/common/Makefile.inc1
-rw-r--r--techlibs/common/gate2lut.v87
-rw-r--r--techlibs/common/simcells.v4
-rw-r--r--techlibs/ice40/synth_ice40.cc18
-rw-r--r--tests/lut/.gitignore1
-rw-r--r--tests/lut/check_map.ys13
-rw-r--r--tests/lut/map_and.v5
-rw-r--r--tests/lut/map_mux.v5
-rw-r--r--tests/lut/map_not.v5
-rw-r--r--tests/lut/map_or.v5
-rw-r--r--tests/lut/map_xor.v5
-rw-r--r--tests/lut/run-test.sh6
12 files changed, 151 insertions, 4 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index ab961ac0b..70074f653 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -25,5 +25,6 @@ $(eval $(call add_share_file,share,techlibs/common/techmap.v))
$(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
$(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
+$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
$(eval $(call add_share_file,share,techlibs/common/cells.lib))
diff --git a/techlibs/common/gate2lut.v b/techlibs/common/gate2lut.v
new file mode 100644
index 000000000..99c123f4a
--- /dev/null
+++ b/techlibs/common/gate2lut.v
@@ -0,0 +1,87 @@
+(* techmap_celltype = "$_NOT_" *)
+module _90_lut_not (A, Y);
+ input A;
+ output Y;
+
+ wire [`LUT_WIDTH-1:0] AA;
+ assign AA = {A};
+
+ \$lut #(
+ .WIDTH(`LUT_WIDTH),
+ .LUT(4'b01)
+ ) lut (
+ .A(AA),
+ .Y(Y)
+ );
+endmodule
+
+(* techmap_celltype = "$_OR_" *)
+module _90_lut_or (A, B, Y);
+ input A, B;
+ output Y;
+
+ wire [`LUT_WIDTH-1:0] AA;
+ assign AA = {B, A};
+
+ \$lut #(
+ .WIDTH(`LUT_WIDTH),
+ .LUT(4'b1110)
+ ) lut (
+ .A(AA),
+ .Y(Y)
+ );
+endmodule
+
+(* techmap_celltype = "$_AND_" *)
+module _90_lut_and (A, B, Y);
+ input A, B;
+ output Y;
+
+ wire [`LUT_WIDTH-1:0] AA;
+ assign AA = {B, A};
+
+ \$lut #(
+ .WIDTH(`LUT_WIDTH),
+ .LUT(4'b1000)
+ ) lut (
+ .A(AA),
+ .Y(Y)
+ );
+endmodule
+
+(* techmap_celltype = "$_XOR_" *)
+module _90_lut_xor (A, B, Y);
+ input A, B;
+ output Y;
+
+ wire [`LUT_WIDTH-1:0] AA;
+ assign AA = {B, A};
+
+ \$lut #(
+ .WIDTH(`LUT_WIDTH),
+ .LUT(4'b0110)
+ ) lut (
+ .A(AA),
+ .Y(Y)
+ );
+endmodule
+
+(* techmap_celltype = "$_MUX_" *)
+module _90_lut_mux (A, B, S, Y);
+ input A, B, S;
+ output Y;
+
+ wire [`LUT_WIDTH-1:0] AA;
+ assign AA = {S, B, A};
+
+ \$lut #(
+ .WIDTH(`LUT_WIDTH),
+ // A 1010 1010
+ // B 1100 1100
+ // S 1111 0000
+ .LUT(8'b_1100_1010)
+ ) lut (
+ .A(AA),
+ .Y(Y)
+ );
+endmodule
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 937512e7c..289673e82 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -465,7 +465,7 @@ endmodule
//-
//- $_SR_NP_ (S, R, Q)
//-
-//- A set-reset latch with negative polarity SET and positive polarioty RESET.
+//- A set-reset latch with negative polarity SET and positive polarity RESET.
//-
//- Truth table: S R | Q
//- -----+---
@@ -489,7 +489,7 @@ endmodule
//-
//- $_SR_PN_ (S, R, Q)
//-
-//- A set-reset latch with positive polarity SET and negative polarioty RESET.
+//- A set-reset latch with positive polarity SET and negative polarity RESET.
//-
//- Truth table: S R | Q
//- -----+---
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index cc4627cd3..931a190e7 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -79,6 +79,9 @@ struct SynthIce40Pass : public ScriptPass
log(" -nobram\n");
log(" do not use SB_RAM40_4K* cells in output netlist\n");
log("\n");
+ log(" -noabc\n");
+ log(" use built-in Yosys LUT techmapping instead of abc\n");
+ log("\n");
log(" -abc2\n");
log(" run two passes of 'abc' for slightly improved logic density\n");
log("\n");
@@ -93,7 +96,7 @@ struct SynthIce40Pass : public ScriptPass
}
string top_opt, blif_file, edif_file, json_file;
- bool nocarry, nodffe, nobram, flatten, retime, relut, abc2, vpr;
+ bool nocarry, nodffe, nobram, flatten, retime, relut, noabc, abc2, vpr;
int min_ce_use;
void clear_flags() YS_OVERRIDE
@@ -109,6 +112,7 @@ struct SynthIce40Pass : public ScriptPass
flatten = true;
retime = false;
relut = false;
+ noabc = false;
abc2 = false;
vpr = false;
}
@@ -177,6 +181,10 @@ struct SynthIce40Pass : public ScriptPass
nobram = true;
continue;
}
+ if (args[argidx] == "-noabc") {
+ noabc = true;
+ continue;
+ }
if (args[argidx] == "-abc2") {
abc2 = true;
continue;
@@ -265,7 +273,13 @@ struct SynthIce40Pass : public ScriptPass
run("ice40_opt", "(only if -abc2)");
}
run("techmap -map +/ice40/latches_map.v");
- run("abc -lut 4");
+ if (noabc || help_mode) {
+ run("simplemap", " (only if -noabc)");
+ run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
+ }
+ if (!noabc) {
+ run("abc -lut 4", "(skip if -noabc)");
+ }
run("clean");
if (relut || help_mode) {
run("ice40_unlut", " (only if -relut)");
diff --git a/tests/lut/.gitignore b/tests/lut/.gitignore
new file mode 100644
index 000000000..397b4a762
--- /dev/null
+++ b/tests/lut/.gitignore
@@ -0,0 +1 @@
+*.log
diff --git a/tests/lut/check_map.ys b/tests/lut/check_map.ys
new file mode 100644
index 000000000..6d659891f
--- /dev/null
+++ b/tests/lut/check_map.ys
@@ -0,0 +1,13 @@
+design -save preopt
+
+simplemap
+techmap -map +/gate2lut.v -D LUT_WIDTH=4
+select -assert-count 1 t:$lut
+design -stash postopt
+
+design -copy-from preopt -as preopt top
+design -copy-from postopt -as postopt top
+equiv_make preopt postopt equiv
+prep -flatten -top equiv
+equiv_induct
+equiv_status -assert
diff --git a/tests/lut/map_and.v b/tests/lut/map_and.v
new file mode 100644
index 000000000..68ae33fd6
--- /dev/null
+++ b/tests/lut/map_and.v
@@ -0,0 +1,5 @@
+module top(...);
+ input a, b;
+ output y;
+ assign y = a&b;
+endmodule
diff --git a/tests/lut/map_mux.v b/tests/lut/map_mux.v
new file mode 100644
index 000000000..ccecf3023
--- /dev/null
+++ b/tests/lut/map_mux.v
@@ -0,0 +1,5 @@
+module top(...);
+ input a, b, s;
+ output y;
+ assign y = s?a:b;
+endmodule
diff --git a/tests/lut/map_not.v b/tests/lut/map_not.v
new file mode 100644
index 000000000..385997414
--- /dev/null
+++ b/tests/lut/map_not.v
@@ -0,0 +1,5 @@
+module top(...);
+ input a;
+ output y;
+ assign y = ~a;
+endmodule
diff --git a/tests/lut/map_or.v b/tests/lut/map_or.v
new file mode 100644
index 000000000..8b8c55188
--- /dev/null
+++ b/tests/lut/map_or.v
@@ -0,0 +1,5 @@
+module top(...);
+ input a, b;
+ output y;
+ assign y = a|b;
+endmodule
diff --git a/tests/lut/map_xor.v b/tests/lut/map_xor.v
new file mode 100644
index 000000000..708a05789
--- /dev/null
+++ b/tests/lut/map_xor.v
@@ -0,0 +1,5 @@
+module top(...);
+ input a, b;
+ output y;
+ assign y = a^b;
+endmodule
diff --git a/tests/lut/run-test.sh b/tests/lut/run-test.sh
new file mode 100644
index 000000000..207417fa6
--- /dev/null
+++ b/tests/lut/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.v; do
+ echo "Running $x.."
+ ../../yosys -q -s check_map.ys -l ${x%.v}.log $x
+done
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 14:39:29 +0000