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-rw-r--r--techlibs/xilinx/abc_ff.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 91cfbc4c4..6f9011ef1 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -94,7 +94,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
wire \$nextQ , \$currQ ;
- \$__ABC_FDCE #(
+ \$__ABC_FDPE #(
.INIT(|0),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),