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-rw-r--r--tests/arch/ice40/bug1597.ys3
-rw-r--r--tests/arch/ice40/ice40_opt.ys1
-rw-r--r--tests/arch/xilinx/abc9_dff.ys7
-rw-r--r--tests/arch/xilinx/opt_lut_ins.ys1
-rw-r--r--tests/arch/xilinx/xilinx_dffopt.ys12
-rw-r--r--tests/opt/opt_dff_en.ys2
-rw-r--r--tests/opt/opt_dff_mux.ys2
-rw-r--r--tests/opt/opt_dff_qd.ys2
-rw-r--r--tests/techmap/dfflegalize_adlatch.ys2
-rw-r--r--tests/techmap/dfflegalize_adlatch_init.ys2
-rw-r--r--tests/techmap/dfflibmap.ys6
-rw-r--r--tests/techmap/dffunmap.ys2
-rw-r--r--tests/techmap/zinit.ys4
13 files changed, 31 insertions, 15 deletions
diff --git a/tests/arch/ice40/bug1597.ys b/tests/arch/ice40/bug1597.ys
index b7983cfa4..73bc18eb2 100644
--- a/tests/arch/ice40/bug1597.ys
+++ b/tests/arch/ice40/bug1597.ys
@@ -3,7 +3,7 @@ module top (
input CLK, PIN_1, PIN_2, PIN_3, PIN_4, PIN_5,
PIN_6, PIN_7, PIN_8, PIN_9, PIN_10, PIN_11, PIN_12, PIN_13, PIN_25,
output USBPU, PIN_14, PIN_15, PIN_16, PIN_17, PIN_18,
- PIN_19, PIN_20, PIN_21, PIN_22, PIN_23, PIN_24,
+ PIN_19,
);
assign USBPU = 0;
@@ -67,6 +67,7 @@ module SSCounter6o (input wire rst, clk, adv, jmp, input wire [5:0] in, output w
SB_LUT4 #(.LUT_INIT(16'h8BB8)) l5 (lo[5], in[5], jmp, out[5], co[4]);
endmodule
EOT
+read_verilog -lib +/ice40/cells_sim.v
hierarchy -top top
flatten
equiv_opt -multiclock -map +/ice40/cells_sim.v synth_ice40
diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys
index 71b68431e..e779ab207 100644
--- a/tests/arch/ice40/ice40_opt.ys
+++ b/tests/arch/ice40/ice40_opt.ys
@@ -21,6 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O);
endmodule
EOT
+read_verilog -icells -lib +/ice40/abc9_model.v +/ice40/cells_sim.v
equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
design -load postopt
select -assert-count 1 t:*
diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys
index 0ba3901f7..79e5a322c 100644
--- a/tests/arch/xilinx/abc9_dff.ys
+++ b/tests/arch/xilinx/abc9_dff.ys
@@ -12,6 +12,7 @@ FDCE_1 #(.INIT(0)) fd7(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[6]));
FDPE_1 #(.INIT(0)) fd8(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[7]));
endmodule
EOT
+read_verilog -lib +/xilinx/cells_sim.v
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 6 t:FD*
@@ -31,6 +32,7 @@ FDCE_1 #(.INIT(0)) fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
FDPE_1 #(.INIT(0)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
endmodule
EOT
+read_verilog -lib +/xilinx/cells_sim.v
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 4 t:FD*
@@ -54,6 +56,7 @@ logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=.*1' with \(\* abc9_flop
logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
logger -expect warning "Whitebox 'FDSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+read_verilog -lib +/xilinx/cells_sim.v
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 8 t:FD*
@@ -75,6 +78,7 @@ always @(posedge clk or posedge pre)
endmodule
EOT
proc
+read_verilog -lib +/xilinx/cells_sim.v
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 1 t:FDCE
@@ -94,6 +98,7 @@ assign q = ~r;
endmodule
EOT
proc
+read_verilog -lib +/xilinx/cells_sim.v
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 1 t:FDRE %co w:r %i
@@ -111,6 +116,7 @@ assign q2 = r;
endmodule
EOT
proc
+read_verilog -lib +/xilinx/cells_sim.v
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 1 t:FDRE %co %a w:r %i
@@ -128,6 +134,7 @@ assign o = r1 | r2;
endmodule
EOT
proc
+read_verilog -lib +/xilinx/cells_sim.v
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
diff --git a/tests/arch/xilinx/opt_lut_ins.ys b/tests/arch/xilinx/opt_lut_ins.ys
index a01d02179..2328919a3 100644
--- a/tests/arch/xilinx/opt_lut_ins.ys
+++ b/tests/arch/xilinx/opt_lut_ins.ys
@@ -18,6 +18,7 @@ end
EOF
+read_verilog -lib +/xilinx/cells_sim.v
equiv_opt -assert -map +/xilinx/cells_sim.v opt_lut_ins -tech xilinx
design -load postopt
diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys
index c09699411..9f0b27ced 100644
--- a/tests/arch/xilinx/xilinx_dffopt.ys
+++ b/tests/arch/xilinx/xilinx_dffopt.ys
@@ -5,7 +5,7 @@ read_verilog << EOT
module t0 (...);
input wire clk;
input wire [7:0] i;
-output wire [7:0] o;
+output wire [0:0] o;
wire [7:0] tmp ;
@@ -52,7 +52,7 @@ read_verilog << EOT
module t0 (...);
input wire clk;
input wire [7:0] i;
-output wire [7:0] o;
+output wire [0:0] o;
wire [7:0] tmp ;
@@ -100,7 +100,7 @@ read_verilog << EOT
module t0 (...);
input wire clk;
input wire [7:0] i;
-output wire [7:0] o;
+output wire [0:0] o;
wire [7:0] tmp ;
@@ -137,7 +137,7 @@ read_verilog << EOT
module t0 (...);
input wire clk;
input wire [7:0] i;
-output wire [7:0] o;
+output wire [0:0] o;
wire [7:0] tmp ;
@@ -183,7 +183,7 @@ read_verilog << EOT
module t0 (...);
input wire clk;
input wire [7:0] i;
-output wire [7:0] o;
+output wire [0:0] o;
wire [7:0] tmp ;
@@ -232,7 +232,7 @@ read_verilog << EOT
module t0 (...);
input wire clk;
input wire [7:0] i;
-output wire [7:0] o;
+output wire [0:0] o;
wire [7:0] tmp ;
diff --git a/tests/opt/opt_dff_en.ys b/tests/opt/opt_dff_en.ys
index 06ee6c63d..9538afcc2 100644
--- a/tests/opt/opt_dff_en.ys
+++ b/tests/opt/opt_dff_en.ys
@@ -6,7 +6,7 @@ module top(...);
input CLK;
input [1:0] D;
-output [15:0] Q;
+output [11:0] Q;
input SRST;
input ARST;
input [1:0] CLR;
diff --git a/tests/opt/opt_dff_mux.ys b/tests/opt/opt_dff_mux.ys
index ed01bed59..f21f9e9b8 100644
--- a/tests/opt/opt_dff_mux.ys
+++ b/tests/opt/opt_dff_mux.ys
@@ -7,7 +7,7 @@ module top(...);
input CLK;
input NE, NS;
input EN;
-output [23:0] Q;
+output [17:0] Q;
input [23:0] D;
input SRST;
input ARST;
diff --git a/tests/opt/opt_dff_qd.ys b/tests/opt/opt_dff_qd.ys
index afc96c42f..7b0b4c224 100644
--- a/tests/opt/opt_dff_qd.ys
+++ b/tests/opt/opt_dff_qd.ys
@@ -7,7 +7,7 @@ module top(...);
input CLK;
input EN;
(* init = 24'h555555 *)
-output [23:0] Q;
+output [19:0] Q;
input SRST;
input ARST;
input [1:0] CLR;
diff --git a/tests/techmap/dfflegalize_adlatch.ys b/tests/techmap/dfflegalize_adlatch.ys
index b242cc809..559363301 100644
--- a/tests/techmap/dfflegalize_adlatch.ys
+++ b/tests/techmap/dfflegalize_adlatch.ys
@@ -12,7 +12,7 @@ $_DLATCH_PN1_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
$_DLATCH_NP1_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
endmodule
-module top(input C, E, R, D, output [13:0] Q);
+module top(input C, E, R, D, output [5:0] Q);
adlatch0 adlatch0_(.E(E), .R(R), .D(D), .Q(Q[2:0]));
adlatch1 adlatch1_(.E(E), .R(R), .D(D), .Q(Q[5:3]));
endmodule
diff --git a/tests/techmap/dfflegalize_adlatch_init.ys b/tests/techmap/dfflegalize_adlatch_init.ys
index a55082d1d..8e371c528 100644
--- a/tests/techmap/dfflegalize_adlatch_init.ys
+++ b/tests/techmap/dfflegalize_adlatch_init.ys
@@ -12,7 +12,7 @@ $_DLATCH_PN1_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
$_DLATCH_NP1_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
endmodule
-module top(input C, E, R, D, output [13:0] Q);
+module top(input C, E, R, D, output [5:0] Q);
adlatch0 adlatch0_(.E(E), .R(R), .D(D), .Q(Q[2:0]));
adlatch1 adlatch1_(.E(E), .R(R), .D(D), .Q(Q[5:3]));
endmodule
diff --git a/tests/techmap/dfflibmap.ys b/tests/techmap/dfflibmap.ys
index 04477eb14..b0a7d6b7e 100644
--- a/tests/techmap/dfflibmap.ys
+++ b/tests/techmap/dfflibmap.ys
@@ -17,9 +17,11 @@ EOT
simplemap
design -save orig
+read_liberty -lib dfflibmap.lib
+
+equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -liberty dfflibmap.lib
+equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dfflibmap.lib
-#equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -liberty dfflibmap.lib
-#equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dfflibmap.lib
dfflibmap -prepare -liberty dfflibmap.lib
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -map-only -liberty dfflibmap.lib
diff --git a/tests/techmap/dffunmap.ys b/tests/techmap/dffunmap.ys
index b813078ee..247699f80 100644
--- a/tests/techmap/dffunmap.ys
+++ b/tests/techmap/dffunmap.ys
@@ -4,7 +4,7 @@ module top(...);
input C, R, E, S;
input [1:0] D;
-output [20:0] Q;
+output [17:0] Q;
$dff #(.CLK_POLARITY(1'b0), .WIDTH(2)) ff0 (.CLK(C), .D(D), .Q(Q[1:0]));
$dffe #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b0), .WIDTH(2)) ff1 (.CLK(C), .EN(E), .D(D), .Q(Q[3:2]));
diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys
index bc07f40e6..af78709b2 100644
--- a/tests/techmap/zinit.ys
+++ b/tests/techmap/zinit.ys
@@ -13,6 +13,8 @@ $_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
$_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
$_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
+assign Q[8] = 0;
+
$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[10:9]));
$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
endmodule
@@ -44,6 +46,8 @@ $_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
$_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
$_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
+assign Q[8] = 0;
+
$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[10:9]));
$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-28 21:13:54 +0000