diff options
| -rw-r--r-- | kernel/rtlil.cc | 6 | ||||
| -rw-r--r-- | passes/tests/test_cell.cc | 4 |
2 files changed, 9 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d7d226942..c56f0dcab 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1035,7 +1035,11 @@ namespace { } if (cell->type.in(ID($shift), ID($shiftx))) { - param_bool(ID::A_SIGNED); + if (cell->type == ID($shiftx)) { + param_bool(ID::A_SIGNED, /*expected=*/false); + } else { + param_bool(ID::A_SIGNED); + } param_bool(ID::B_SIGNED); port(ID::A, param(ID::A_WIDTH)); port(ID::B, param(ID::B_WIDTH)); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index bdb475d3b..228b6b67a 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -264,6 +264,10 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->setPort(ID::Y, wire); } + if (cell_type.in(ID($shiftx))) { + cell->parameters[ID::A_SIGNED] = false; + } + if (cell_type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) { cell->parameters[ID::B_SIGNED] = false; } |