diff options
| -rw-r--r-- | techlibs/common/simlib.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 09ffa9a68..3c931c813 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -108,12 +108,13 @@ parameter Y_WIDTH = 0; input [A_WIDTH-1:0] A; output [Y_WIDTH-1:0] Y; +wire [Y_WIDTH-1:0] tmp; generate if (A_SIGNED) begin:BLOCK1 - assign Y = -$signed(A); + assign tmp = $signed(A), Y = -tmp; end else begin:BLOCK2 - assign Y = -A; + assign tmp = A, Y = -tmp; end endgenerate |