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-rw-r--r--tests/techmap/techmap_replace.ys2
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
index ee5c6bc7e..c2f42d50b 100644
--- a/tests/techmap/techmap_replace.ys
+++ b/tests/techmap/techmap_replace.ys
@@ -2,6 +2,7 @@ read_verilog <<EOT
module sub(input i, output o, input j);
foobar _TECHMAP_REPLACE_(i, o, j);
wire _TECHMAP_REPLACE_.asdf = i ;
+barfoo _TECHMAP_REPLACE_.blah (i, o, j);
endmodule
EOT
design -stash techmap
@@ -14,3 +15,4 @@ EOT
techmap -map %techmap
select -assert-any w:s0.asdf
+select -assert-any c:s0.blah