diff options
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/abc9.cc | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index be900f0e7..77659b4d8 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -284,7 +284,7 @@ struct XAigerWriter toposort.node(cell->name); - if (inst_module->attributes.count("\\abc9_flop")) + if (inst_module->get_bool_attribute("\\abc9_flop")) flop_boxes.push_back(cell); continue; } diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 3c53a5223..d6c8260b2 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -533,7 +533,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip } RTLIL::Module* box_module = design->module(mapped_cell->type); - auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop"); + auto abc9_flop = box_module && box_module->get_bool_attribute("\\abc9_flop"); for (auto &conn : mapped_cell->connections()) { RTLIL::SigSpec newsig; for (auto c : conn.second.chunks()) { @@ -988,7 +988,7 @@ struct Abc9Pass : public Pass { for (auto cell : all_cells) { auto inst_module = design->module(cell->type); - if (!inst_module || !inst_module->attributes.count("\\abc9_flop") + if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop") || cell->get_bool_attribute("\\abc9_keep")) continue; |