aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--passes/pmgen/xilinx_dsp.cc10
-rw-r--r--passes/pmgen/xilinx_dsp.pmg12
2 files changed, 18 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 055b3d6aa..5d50c7795 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -451,6 +451,16 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
P.replace(pm.sigmap(D), Q);
st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
+ for (auto c : Q.chunks()) {
+ auto it = c.wire->attributes.find("\\init");
+ if (it == c.wire->attributes.end())
+ continue;
+ for (int i = c.offset; i < c.offset+c.width; i++) {
+ log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
+ it->second[i] = State::Sx;
+ }
+ }
+
cell->setParam("\\PREG", State::S1);
}
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 05837d057..7db8e95a6 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -290,8 +290,8 @@ endmatch
code argQ
if (ff) {
- for (auto b : argQ)
- if (b.wire->get_bool_attribute(\keep))
+ for (auto c : argQ.chunks())
+ if (c.wire->get_bool_attribute(\keep))
reject;
if (clock != SigBit()) {
@@ -447,9 +447,13 @@ code
if (dff) {
dffQ = port(dff, \Q);
- for (auto b : dffQ)
- if (b.wire->get_bool_attribute(\keep))
+ for (auto c : dffQ.chunks()) {
+ if (c.wire->get_bool_attribute(\keep))
reject;
+ Const init = c.wire->attributes.at(\init, State::Sx);
+ if (!init.is_fully_undef() && !init.is_fully_zero())
+ reject;
+ }
if (clock != SigBit()) {
if (port(dff, \CLK) != clock)