diff options
| -rw-r--r-- | passes/techmap/abc9.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index b32facc48..492911177 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -455,9 +455,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w)); if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx; design->select(module, remap_wire); - RTLIL::Wire *wire = module->wire(w->name); if (w->port_output) { - for (int i = 0; i < GetSize(remap_wire); i++) + RTLIL::Wire *wire = module->wire(w->name); + for (int i = 0; i < GetSize(wire); i++) output_bits.insert({wire, i}); } } |