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Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
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@@ -381,9 +381,6 @@ Verilog Attributes and non-standard features - The module attribute ``abc9_flop`` is a boolean marking the module as a whitebox that describes the synchronous behaviour of a flip-flop. -- The cell attribute ``abc9_keep`` is a boolean indicating that this black/ - white box should be preserved through `abc9` mapping. - - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks according to the type of the always. These are checked for correctness in |