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-rw-r--r--backends/aiger/xaiger.cc77
1 files changed, 45 insertions, 32 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 627133314..445103771 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -81,8 +81,7 @@ struct XAigerWriter
pool<SigBit> input_bits, output_bits;
dict<SigBit, SigBit> not_map, alias_map;
dict<SigBit, pair<SigBit, SigBit>> and_map;
- vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
- vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
+ vector<SigBit> ci_bits, co_bits;
dict<SigBit, float> arrival_times;
vector<pair<int, int>> aig_gates;
@@ -367,7 +366,6 @@ struct XAigerWriter
cell->setPort(port_name, rhs);
}
- int offset = 0;
for (auto b : rhs.bits()) {
SigBit I = sigmap(b);
if (b == RTLIL::Sx)
@@ -378,7 +376,7 @@ struct XAigerWriter
else
alias_map[b] = I;
}
- co_bits.emplace_back(b, cell, port_name, offset++, 0);
+ co_bits.emplace_back(b);
unused_bits.erase(b);
}
}
@@ -398,9 +396,8 @@ struct XAigerWriter
cell->setPort(port_name, rhs);
}
- int offset = 0;
for (const auto &b : rhs.bits()) {
- ci_bits.emplace_back(b, cell, port_name, offset++);
+ ci_bits.emplace_back(b);
SigBit O = sigmap(b);
if (O != b)
alias_map[O] = b;
@@ -487,15 +484,13 @@ struct XAigerWriter
aig_map[bit] = 2*aig_m;
}
- for (auto &c : ci_bits) {
- RTLIL::SigBit bit = std::get<0>(c);
+ for (auto bit : ci_bits) {
aig_m++, aig_i++;
aig_map[bit] = 2*aig_m;
}
- for (auto &c : co_bits) {
- RTLIL::SigBit bit = std::get<0>(c);
- std::get<4>(c) = ordered_outputs[bit] = aig_o++;
+ for (auto bit : co_bits) {
+ ordered_outputs[bit] = aig_o++;
aig_outputs.push_back(bit2aig(bit));
}
@@ -508,7 +503,6 @@ struct XAigerWriter
ordered_outputs[bit] = aig_o++;
aig_outputs.push_back(bit2aig(bit));
}
-
}
void write_aiger(std::ostream &f, bool ascii_mode)
@@ -605,25 +599,46 @@ struct XAigerWriter
RTLIL::Module *holes_module = module->design->addModule("$__holes__");
log_assert(holes_module);
+ dict<IdString, Cell*> cell_cache;
+
int port_id = 1;
int box_count = 0;
for (auto cell : box_list) {
- RTLIL::Module* box_module = module->design->module(cell->type);
+ RTLIL::Module* orig_box_module = module->design->module(cell->type);
+ log_assert(orig_box_module);
+ IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
+ RTLIL::Module* box_module = module->design->module(derived_name);
+ if (box_module->has_processes())
+ log_error("ABC9 box '%s' contains processes!\n", box_module->name.c_str());
+
int box_inputs = 0, box_outputs = 0;
- Cell *holes_cell = nullptr;
- if (box_module->get_bool_attribute("\\whitebox")) {
+ auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
+ Cell *holes_cell = r.first->second;
+ if (r.second && box_module->get_bool_attribute("\\whitebox")) {
holes_cell = holes_module->addCell(cell->name, cell->type);
holes_cell->parameters = cell->parameters;
+ r.first->second = holes_cell;
+
+ // Since Module::derive() will create a new module, there
+ // is a chance that the ports will be alphabetically ordered
+ // again, which is a problem when carry-chains are involved.
+ // Inherit the port ordering from the original module here...
+ // (and set the port_id below, when iterating through those)
+ log_assert(GetSize(box_module->ports) == GetSize(orig_box_module->ports));
+ box_module->ports = orig_box_module->ports;
}
// NB: Assume box_module->ports are sorted alphabetically
// (as RTLIL::Module::fixup_ports() would do)
+ int box_port_id = 1;
for (const auto &port_name : box_module->ports) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
+ if (r.second)
+ w->port_id = box_port_id++;
RTLIL::Wire *holes_wire;
- RTLIL::SigSpec port_wire;
- if (w->port_input) {
+ RTLIL::SigSpec port_sig;
+ if (w->port_input)
for (int i = 0; i < GetSize(w); i++) {
box_inputs++;
holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
@@ -634,28 +649,29 @@ struct XAigerWriter
holes_module->ports.push_back(holes_wire->name);
}
if (holes_cell)
- port_wire.append(holes_wire);
+ port_sig.append(holes_wire);
}
- if (!port_wire.empty())
- holes_cell->setPort(w->name, port_wire);
- }
if (w->port_output) {
box_outputs += GetSize(w);
for (int i = 0; i < GetSize(w); i++) {
if (GetSize(w) == 1)
- holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
+ holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), log_id(w->name)));
else
- holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
+ holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
holes_wire->port_output = true;
holes_wire->port_id = port_id++;
holes_module->ports.push_back(holes_wire->name);
if (holes_cell)
- port_wire.append(holes_wire);
+ port_sig.append(holes_wire);
else
holes_module->connect(holes_wire, State::S0);
}
- if (!port_wire.empty())
- holes_cell->setPort(w->name, port_wire);
+ }
+ if (!port_sig.empty()) {
+ if (r.second)
+ holes_cell->setPort(w->name, port_sig);
+ else
+ holes_module->connect(holes_cell->getPort(w->name), port_sig);
}
}
@@ -685,14 +701,11 @@ struct XAigerWriter
RTLIL::Selection& sel = holes_module->design->selection_stack.back();
sel.select(holes_module);
- // TODO: Should not need to opt_merge if we only instantiate
- // each box type once...
- Pass::call(holes_module->design, "opt_merge -share_all");
-
Pass::call(holes_module->design, "flatten -wb");
- // TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
- // instead of per write_xaiger call
+ // Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
+ // since boxes may contain parameters in which case `flatten` would have
+ // created a new $paramod ...
Pass::call(holes_module->design, "techmap");
Pass::call(holes_module->design, "aigmap");
for (auto cell : holes_module->cells())
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 04:25:52 +0000