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-rw-r--r--backends/aiger/xaiger.cc14
1 files changed, 8 insertions, 6 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 48e902666..637c54ff9 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -86,14 +86,15 @@ struct XAigerWriter
int bit2aig(SigBit bit)
{
- // NB: Cannot use iterator returned from aig_map.insert()
- // since this function is called recursively
auto it = aig_map.find(bit);
if (it != aig_map.end()) {
log_assert(it->second >= 0);
return it->second;
}
+ // NB: Cannot use iterator returned from aig_map.insert()
+ // since this function is called recursively
+
int a = -1;
if (not_map.count(bit)) {
a = bit2aig(not_map.at(bit)) ^ 1;
@@ -109,7 +110,7 @@ struct XAigerWriter
}
if (bit == State::Sx || bit == State::Sz) {
- log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit));
+ log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
a = aig_map.at(State::S0);
}
@@ -428,12 +429,13 @@ struct XAigerWriter
module->connect(new_bit, bit);
if (not_map.count(bit))
not_map[new_bit] = not_map.at(bit);
- else if (and_map.count(bit))
- and_map[new_bit] = and_map.at(bit);
+ else if (and_map.count(bit)) {
+ //and_map[new_bit] = and_map.at(bit); // Breaks gcc-4.8
+ and_map.insert(std::make_pair(new_bit, and_map.at(bit)));
+ }
else if (alias_map.count(bit))
alias_map[new_bit] = alias_map.at(bit);
else
- //log_abort();
alias_map[new_bit] = bit;
output_bits.erase(bit);
output_bits.insert(new_bit);