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-rw-r--r--backends/cxxrtl/cxxrtl.h29
-rw-r--r--backends/cxxrtl/cxxrtl_backend.cc60
-rw-r--r--backends/cxxrtl/cxxrtl_capi.cc4
-rw-r--r--backends/cxxrtl/cxxrtl_capi.h8
4 files changed, 92 insertions, 9 deletions
diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h
index 7d3a8485c..eb7d7eaeb 100644
--- a/backends/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/cxxrtl.h
@@ -110,9 +110,11 @@ struct value : public expr_base<value<Bits>> {
explicit constexpr value(Init ...init) : data{init...} {}
value(const value<Bits> &) = default;
- value(value<Bits> &&) = default;
value<Bits> &operator=(const value<Bits> &) = default;
+ value(value<Bits> &&) = default;
+ value<Bits> &operator=(value<Bits> &&) = default;
+
// A (no-op) helper that forces the cast to value<>.
CXXRTL_ALWAYS_INLINE
const value<Bits> &val() const {
@@ -661,10 +663,16 @@ struct wire {
template<typename... Init>
explicit constexpr wire(Init ...init) : curr{init...}, next{init...} {}
+ // Copying and copy-assigning values is natural. If, however, a value is replaced with a wire,
+ // e.g. because a module is built with a different optimization level, then existing code could
+ // unintentionally copy a wire instead, which would create a subtle but serious bug. To make sure
+ // this doesn't happen, prohibit copying and copy-assigning wires.
wire(const wire<Bits> &) = delete;
- wire(wire<Bits> &&) = default;
wire<Bits> &operator=(const wire<Bits> &) = delete;
+ wire(wire<Bits> &&) = default;
+ wire<Bits> &operator=(wire<Bits> &&) = default;
+
template<class IntegerT>
CXXRTL_ALWAYS_INLINE
IntegerT get() const {
@@ -706,6 +714,9 @@ struct memory {
memory(const memory<Width> &) = delete;
memory<Width> &operator=(const memory<Width> &) = delete;
+ memory(memory<Width> &&) = default;
+ memory<Width> &operator=(memory<Width> &&) = default;
+
// The only way to get the compiler to put the initializer in .rodata and do not copy it on stack is to stuff it
// into a plain array. You'd think an std::initializer_list would work here, but it doesn't, because you can't
// construct an initializer_list in a constexpr (or something) and so if you try to do that the whole thing is
@@ -829,7 +840,7 @@ struct metadata {
typedef std::map<std::string, metadata> metadata_map;
-// Helper class to disambiguate values/wires and their aliases.
+// Tag class to disambiguate values/wires and their aliases.
struct debug_alias {};
// This structure is intended for consumption via foreign function interfaces, like Python's ctypes.
@@ -979,13 +990,25 @@ struct debug_items {
}
};
+// Tag class to disambiguate module move constructor and module constructor that takes black boxes
+// out of another instance of the module.
+struct adopt {};
+
struct module {
module() {}
virtual ~module() {}
+ // Modules with black boxes cannot be copied. Although not all designs include black boxes,
+ // delete the copy constructor and copy assignment operator to make sure that any downstream
+ // code that manipulates modules doesn't accidentally depend on their availability.
module(const module &) = delete;
module &operator=(const module &) = delete;
+ module(module &&) = default;
+ module &operator=(module &&) = default;
+
+ virtual void reset() = 0;
+
virtual bool eval() = 0;
virtual bool commit() = 0;
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 23ea57b5a..7efb0aeaf 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -1036,8 +1036,12 @@ struct CxxrtlWorker {
// Edge-sensitive logic
RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
- f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
- << mangle(clk_bit) << ") {\n";
+ if (clk_bit.wire) {
+ f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
+ << mangle(clk_bit) << ") {\n";
+ } else {
+ f << indent << "if (false) {\n";
+ }
inc_indent();
if (cell->hasPort(ID::EN)) {
f << indent << "if (";
@@ -1130,8 +1134,12 @@ struct CxxrtlWorker {
if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
- f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
- << mangle(clk_bit) << ") {\n";
+ if (clk_bit.wire) {
+ f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
+ << mangle(clk_bit) << ") {\n";
+ } else {
+ f << indent << "if (false) {\n";
+ }
inc_indent();
}
RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
@@ -1869,6 +1877,46 @@ struct CxxrtlWorker {
}
if (has_cells)
f << "\n";
+ f << indent << mangle(module) << "() {}\n";
+ if (has_cells) {
+ f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) :\n";
+ bool first = true;
+ for (auto cell : module->cells()) {
+ if (is_internal_cell(cell->type))
+ continue;
+ if (first) {
+ first = false;
+ } else {
+ f << ",\n";
+ }
+ RTLIL::Module *cell_module = module->design->module(cell->type);
+ if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
+ f << indent << " " << mangle(cell) << "(std::move(other." << mangle(cell) << "))";
+ } else {
+ f << indent << " " << mangle(cell) << "(adopt {}, std::move(other." << mangle(cell) << "))";
+ }
+ }
+ f << " {\n";
+ inc_indent();
+ for (auto cell : module->cells()) {
+ if (is_internal_cell(cell->type))
+ continue;
+ RTLIL::Module *cell_module = module->design->module(cell->type);
+ if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
+ f << indent << mangle(cell) << "->reset();\n";
+ }
+ dec_indent();
+ f << indent << "}\n";
+ } else {
+ f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) {}\n";
+ }
+ f << "\n";
+ f << indent << "void reset() override {\n";
+ inc_indent();
+ f << indent << "*this = " << mangle(module) << "(adopt {}, std::move(*this));\n";
+ dec_indent();
+ f << indent << "}\n";
+ f << "\n";
f << indent << "bool eval() override;\n";
f << indent << "bool commit() override;\n";
if (debug_info)
@@ -2105,14 +2153,14 @@ struct CxxrtlWorker {
// Various DFF cells are treated like posedge/negedge processes, see above for details.
if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
- if (cell->getPort(ID::CLK).is_wire())
+ if (sigmap(cell->getPort(ID::CLK)).is_wire())
register_edge_signal(sigmap, cell->getPort(ID::CLK),
cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
}
// Similar for memory port cells.
if (cell->type.in(ID($memrd), ID($memwr))) {
if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
- if (cell->getPort(ID::CLK).is_wire())
+ if (sigmap(cell->getPort(ID::CLK)).is_wire())
register_edge_signal(sigmap, cell->getPort(ID::CLK),
cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
}
diff --git a/backends/cxxrtl/cxxrtl_capi.cc b/backends/cxxrtl/cxxrtl_capi.cc
index b77e4c491..1c3c63e3e 100644
--- a/backends/cxxrtl/cxxrtl_capi.cc
+++ b/backends/cxxrtl/cxxrtl_capi.cc
@@ -43,6 +43,10 @@ void cxxrtl_destroy(cxxrtl_handle handle) {
delete handle;
}
+void cxxrtl_reset(cxxrtl_handle handle) {
+ handle->module->reset();
+}
+
int cxxrtl_eval(cxxrtl_handle handle) {
return handle->module->eval();
}
diff --git a/backends/cxxrtl/cxxrtl_capi.h b/backends/cxxrtl/cxxrtl_capi.h
index 385d6dcf3..662bf2c20 100644
--- a/backends/cxxrtl/cxxrtl_capi.h
+++ b/backends/cxxrtl/cxxrtl_capi.h
@@ -55,6 +55,14 @@ cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design);
// Release all resources used by a design and its handle.
void cxxrtl_destroy(cxxrtl_handle handle);
+// Reinitialize the design, replacing the internal state with the reset values while preserving
+// black boxes.
+//
+// This operation is essentially equivalent to a power-on reset. Values, wires, and memories are
+// returned to their reset state while preserving the state of black boxes and keeping all of
+// the interior pointers obtained with e.g. `cxxrtl_get` valid.
+void cxxrtl_reset(cxxrtl_handle handle);
+
// Evaluate the design, propagating changes on inputs to the `next` value of internal state and
// output wires.
//
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 14:31:39 +0000