diff options
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index b9d5e5ec2..d733bdc5a 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -941,9 +941,9 @@ struct VerilogBackend : public Backend { log(" without this option all internal cells are converted to verilog\n"); log(" expressions.\n"); log("\n"); - log(" -placeholders\n"); - log(" usually modules with the 'placeholder' attribute are ignored. with\n"); - log(" this option set only the modules with the 'placeholder' attribute\n"); + log(" -blackboxes\n"); + log(" usually modules with the 'blackbox' attribute are ignored. with\n"); + log(" this option set only the modules with the 'blackbox' attribute\n"); log(" are written to the output file.\n"); log("\n"); log(" -selected\n"); @@ -960,7 +960,7 @@ struct VerilogBackend : public Backend { attr2comment = false; noexpr = false; - bool placeholders = false; + bool blackboxes = false; bool selected = false; reg_ct.clear(); @@ -988,8 +988,8 @@ struct VerilogBackend : public Backend { noexpr = true; continue; } - if (arg == "-placeholders") { - placeholders = true; + if (arg == "-blackboxes") { + blackboxes = true; continue; } if (arg == "-selected") { @@ -1002,7 +1002,7 @@ struct VerilogBackend : public Backend { fprintf(f, "/* Generated by %s */\n", yosys_version_str); for (auto it = design->modules.begin(); it != design->modules.end(); it++) { - if (it->second->get_bool_attribute("\\placeholder") != placeholders) + if (it->second->get_bool_attribute("\\blackbox") != blackboxes) continue; if (selected && !design->selected_whole_module(it->first)) { if (design->selected_module(it->first)) |