diff options
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/blif/blif.cc | 1 | ||||
| -rw-r--r-- | backends/edif/edif.cc | 1 | ||||
| -rw-r--r-- | backends/intersynth/intersynth.cc | 2 | ||||
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 3 |
4 files changed, 0 insertions, 7 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index a240d2a26..d0c250790 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -70,7 +70,6 @@ struct BlifDumper const char *cstr(RTLIL::SigSpec sig) { - sig.optimize(); log_assert(sig.size() == 1); if (sig.chunks().at(0).wire == NULL) diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 3b9a43370..8f36f4090 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -315,7 +315,6 @@ struct EdifBackend : public Backend { } for (auto &it : net_join_db) { RTLIL::SigSpec sig = it.first; - sig.optimize(); log_assert(sig.size() == 1); if (sig.chunks().at(0).wire == NULL) { if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1) diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 832922def..a4cad5add 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -28,8 +28,6 @@ static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig) { - sig.optimize(); - if (sig.chunks().size() != 1) error: log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig)); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 160835087..1dcc3003a 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -133,7 +133,6 @@ std::string id(std::string internal_id, bool may_rename = true) bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) { - sig.optimize(); if (sig.chunks().size() != 1 || sig.chunks()[0].wire == NULL) return false; if (reg_wires.count(sig.chunks()[0].wire->name) == 0) @@ -303,7 +302,6 @@ std::string cellname(RTLIL::Cell *cell) if (sig.size() != 1 || sig.is_fully_const()) goto no_special_reg_name; - sig.optimize(); RTLIL::Wire *wire = sig.chunks()[0].wire; if (wire->name[0] != '\\') @@ -909,7 +907,6 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) continue; RTLIL::SigSpec sig = cell->connections["\\Q"]; - sig.optimize(); if (sig.chunks().size() == 1 && sig.chunks()[0].wire) for (int i = 0; i < sig.chunks()[0].width; i++) |