diff options
Diffstat (limited to 'frontends/verilog')
-rw-r--r-- | frontends/verilog/verilog_frontend.cc | 10 | ||||
-rw-r--r-- | frontends/verilog/verilog_parser.y | 2 |
2 files changed, 10 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 87ea8c6ae..8ec347e89 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -75,6 +75,9 @@ struct VerilogFrontend : public Frontend { log(" -dump_vlog\n"); log(" dump ast as Verilog code (after simplification)\n"); log("\n"); + log(" -dump_rtlil\n"); + log(" dump generated RTLIL netlist\n"); + log("\n"); log(" -yydebug\n"); log(" enable parser debug output\n"); log("\n"); @@ -168,6 +171,7 @@ struct VerilogFrontend : public Frontend { bool flag_dump_ast1 = false; bool flag_dump_ast2 = false; bool flag_dump_vlog = false; + bool flag_dump_rtlil = false; bool flag_nolatches = false; bool flag_nomeminit = false; bool flag_nomem2reg = false; @@ -216,6 +220,10 @@ struct VerilogFrontend : public Frontend { flag_dump_vlog = true; continue; } + if (arg == "-dump_rtlil") { + flag_dump_rtlil = true; + continue; + } if (arg == "-yydebug") { frontend_verilog_yydebug = true; continue; @@ -342,7 +350,7 @@ struct VerilogFrontend : public Frontend { if (flag_nodpi) error_on_dpi_function(current_ast); - AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire); + AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire); if (!flag_nopp) delete lexin; diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4cb65a088..c2327011f 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1219,7 +1219,7 @@ rvalue: $$ = new AstNode(AST_IDENTIFIER, $2); $$->str = *$1; delete $1; - if ($2 == nullptr && $$->str == "\\$initstate") + if ($2 == nullptr && formal_mode && ($$->str == "\\$initstate" || $$->str == "\\$anyconst" || $$->str == "\\$aconst")) $$->type = AST_FCALL; } | hierarchical_id non_opt_multirange { |