aboutsummaryrefslogtreecommitdiffstats
path: root/kernel/celltypes.h
diff options
context:
space:
mode:
Diffstat (limited to 'kernel/celltypes.h')
-rw-r--r--kernel/celltypes.h122
1 files changed, 75 insertions, 47 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 85c21ef3c..533c370fe 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -27,13 +27,13 @@ YOSYS_NAMESPACE_BEGIN
struct CellType
{
RTLIL::IdString type;
- std::set<RTLIL::IdString> inputs, outputs;
+ pool<RTLIL::IdString> inputs, outputs;
bool is_evaluable;
};
struct CellTypes
{
- std::map<RTLIL::IdString, CellType> cell_types;
+ dict<RTLIL::IdString, CellType> cell_types;
CellTypes()
{
@@ -55,7 +55,7 @@ struct CellTypes
setup_stdcells_mem();
}
- void setup_type(RTLIL::IdString type, const std::set<RTLIL::IdString> &inputs, const std::set<RTLIL::IdString> &outputs, bool is_evaluable = false)
+ void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)
{
CellType ct = {type, inputs, outputs, is_evaluable};
cell_types[ct.type] = ct;
@@ -63,7 +63,7 @@ struct CellTypes
void setup_module(RTLIL::Module *module)
{
- std::set<RTLIL::IdString> inputs, outputs;
+ pool<RTLIL::IdString> inputs, outputs;
for (RTLIL::IdString wire_name : module->ports) {
RTLIL::Wire *wire = module->wire(wire_name);
if (wire->port_input)
@@ -96,82 +96,105 @@ struct CellTypes
"$logic_and", "$logic_or", "$concat", "$macc"
};
+ IdString A = "\\A", B = "\\B", S = "\\S", Y = "\\Y";
+ IdString P = "\\P", G = "\\G", C = "\\C", X = "\\X";
+ IdString BI = "\\BI", CI = "\\CI", CO = "\\CO", EN = "\\EN";
+
for (auto type : unary_ops)
- setup_type(type, {"\\A"}, {"\\Y"}, true);
+ setup_type(type, {A}, {Y}, true);
for (auto type : binary_ops)
- setup_type(type, {"\\A", "\\B"}, {"\\Y"}, true);
+ setup_type(type, {A, B}, {Y}, true);
for (auto type : std::vector<RTLIL::IdString>({"$mux", "$pmux"}))
- setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, true);
+ setup_type(type, {A, B, S}, {Y}, true);
- setup_type("$lcu", {"\\P", "\\G", "\\CI"}, {"\\CO"}, true);
- setup_type("$alu", {"\\A", "\\B", "\\CI", "\\BI"}, {"\\X", "\\Y", "\\CO"}, true);
- setup_type("$fa", {"\\A", "\\B", "\\C"}, {"\\X", "\\Y"}, true);
+ setup_type("$lcu", {P, G, CI}, {CO}, true);
+ setup_type("$alu", {A, B, CI, BI}, {X, Y, CO}, true);
+ setup_type("$fa", {A, B, C}, {X, Y}, true);
- setup_type("$assert", {"\\A", "\\EN"}, std::set<RTLIL::IdString>(), true);
+ setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
+ setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
+ setup_type("$equiv", {A, B}, {Y}, true);
}
void setup_internals_mem()
{
- setup_type("$sr", {"\\SET", "\\CLR"}, {"\\Q"});
- setup_type("$dff", {"\\CLK", "\\D"}, {"\\Q"});
- setup_type("$dffsr", {"\\CLK", "\\SET", "\\CLR", "\\D"}, {"\\Q"});
- setup_type("$adff", {"\\CLK", "\\ARST", "\\D"}, {"\\Q"});
- setup_type("$dlatch", {"\\EN", "\\D"}, {"\\Q"});
- setup_type("$dlatchsr", {"\\EN", "\\SET", "\\CLR", "\\D"}, {"\\Q"});
-
- setup_type("$memrd", {"\\CLK", "\\ADDR"}, {"\\DATA"});
- setup_type("$memwr", {"\\CLK", "\\EN", "\\ADDR", "\\DATA"}, std::set<RTLIL::IdString>());
- setup_type("$mem", {"\\RD_CLK", "\\RD_ADDR", "\\WR_CLK", "\\WR_EN", "\\WR_ADDR", "\\WR_DATA"}, {"\\RD_DATA"});
-
- setup_type("$fsm", {"\\CLK", "\\ARST", "\\CTRL_IN"}, {"\\CTRL_OUT"});
+ IdString SET = "\\SET", CLR = "\\CLR", CLK = "\\CLK", ARST = "\\ARST", EN = "\\EN";
+ IdString Q = "\\Q", D = "\\D", ADDR = "\\ADDR", DATA = "\\DATA";
+ IdString RD_CLK = "\\RD_CLK", RD_ADDR = "\\RD_ADDR", WR_CLK = "\\WR_CLK", WR_EN = "\\WR_EN";
+ IdString WR_ADDR = "\\WR_ADDR", WR_DATA = "\\WR_DATA", RD_DATA = "\\RD_DATA";
+ IdString CTRL_IN = "\\CTRL_IN", CTRL_OUT = "\\CTRL_OUT";
+
+ setup_type("$sr", {SET, CLR}, {Q});
+ setup_type("$dff", {CLK, D}, {Q});
+ setup_type("$dffe", {CLK, EN, D}, {Q});
+ setup_type("$dffsr", {CLK, SET, CLR, D}, {Q});
+ setup_type("$adff", {CLK, ARST, D}, {Q});
+ setup_type("$dlatch", {EN, D}, {Q});
+ setup_type("$dlatchsr", {EN, SET, CLR, D}, {Q});
+
+ setup_type("$memrd", {CLK, ADDR}, {DATA});
+ setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>());
+ setup_type("$meminit", {ADDR, DATA}, pool<RTLIL::IdString>());
+ setup_type("$mem", {RD_CLK, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA});
+
+ setup_type("$fsm", {CLK, ARST, CTRL_IN}, {CTRL_OUT});
}
void setup_stdcells()
{
- setup_type("$_NOT_", {"\\A"}, {"\\Y"}, true);
- setup_type("$_AND_", {"\\A", "\\B"}, {"\\Y"}, true);
- setup_type("$_NAND_", {"\\A", "\\B"}, {"\\Y"}, true);
- setup_type("$_OR_", {"\\A", "\\B"}, {"\\Y"}, true);
- setup_type("$_NOR_", {"\\A", "\\B"}, {"\\Y"}, true);
- setup_type("$_XOR_", {"\\A", "\\B"}, {"\\Y"}, true);
- setup_type("$_XNOR_", {"\\A", "\\B"}, {"\\Y"}, true);
- setup_type("$_MUX_", {"\\A", "\\B", "\\S"}, {"\\Y"}, true);
- setup_type("$_AOI3_", {"\\A", "\\B", "\\C"}, {"\\Y"}, true);
- setup_type("$_OAI3_", {"\\A", "\\B", "\\C"}, {"\\Y"}, true);
- setup_type("$_AOI4_", {"\\A", "\\B", "\\C", "\\D"}, {"\\Y"}, true);
- setup_type("$_OAI4_", {"\\A", "\\B", "\\C", "\\D"}, {"\\Y"}, true);
+ IdString A = "\\A", B = "\\B", C = "\\C", D = "\\D", S = "\\S", Y = "\\Y";
+ setup_type("$_BUF_", {A}, {Y}, true);
+ setup_type("$_NOT_", {A}, {Y}, true);
+ setup_type("$_AND_", {A, B}, {Y}, true);
+ setup_type("$_NAND_", {A, B}, {Y}, true);
+ setup_type("$_OR_", {A, B}, {Y}, true);
+ setup_type("$_NOR_", {A, B}, {Y}, true);
+ setup_type("$_XOR_", {A, B}, {Y}, true);
+ setup_type("$_XNOR_", {A, B}, {Y}, true);
+ setup_type("$_MUX_", {A, B, S}, {Y}, true);
+ setup_type("$_AOI3_", {A, B, C}, {Y}, true);
+ setup_type("$_OAI3_", {A, B, C}, {Y}, true);
+ setup_type("$_AOI4_", {A, B, C, D}, {Y}, true);
+ setup_type("$_OAI4_", {A, B, C, D}, {Y}, true);
}
void setup_stdcells_mem()
{
+ IdString S = "\\S", R = "\\R", C = "\\C";
+ IdString D = "\\D", Q = "\\Q", E = "\\E";
+
std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
for (auto c1 : list_np)
for (auto c2 : list_np)
- setup_type(stringf("$_SR_%c%c_", c1, c2), {"\\S", "\\R"}, {"\\Q"});
+ setup_type(stringf("$_SR_%c%c_", c1, c2), {S, R}, {Q});
+
+ for (auto c1 : list_np)
+ setup_type(stringf("$_DFF_%c_", c1), {C, D}, {Q});
for (auto c1 : list_np)
- setup_type(stringf("$_DFF_%c_", c1), {"\\C", "\\D"}, {"\\Q"});
+ for (auto c2 : list_np)
+ setup_type(stringf("$_DFFE_%c%c_", c1, c2), {C, D, E}, {Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
- setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {"\\C", "\\R", "\\D"}, {"\\Q"});
+ setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {C, R, D}, {Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_np)
- setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {"\\C", "\\S", "\\R", "\\D"}, {"\\Q"});
+ setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {C, S, R, D}, {Q});
for (auto c1 : list_np)
- setup_type(stringf("$_DLATCH_%c_", c1), {"\\E", "\\D"}, {"\\Q"});
+ setup_type(stringf("$_DLATCH_%c_", c1), {E, D}, {Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_np)
- setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {"\\E", "\\S", "\\R", "\\D"}, {"\\Q"});
+ setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {E, S, R, D}, {Q});
}
void clear()
@@ -261,6 +284,8 @@ struct CellTypes
HANDLE_CELL_TYPE(neg)
#undef HANDLE_CELL_TYPE
+ if (type == "$_BUF_")
+ return arg1;
if (type == "$_NOT_")
return eval_not(arg1);
if (type == "$_AND_")
@@ -300,7 +325,7 @@ struct CellTypes
int width = cell->parameters.at("\\WIDTH").as_int();
std::vector<RTLIL::State> t = cell->parameters.at("\\LUT").bits;
- while (SIZE(t) < (1 << width))
+ while (GetSize(t) < (1 << width))
t.push_back(RTLIL::S0);
t.resize(1 << width);
@@ -308,16 +333,16 @@ struct CellTypes
RTLIL::State sel = arg1.bits.at(i);
std::vector<RTLIL::State> new_t;
if (sel == RTLIL::S0)
- new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + SIZE(t)/2);
+ new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
else if (sel == RTLIL::S1)
- new_t = std::vector<RTLIL::State>(t.begin() + SIZE(t)/2, t.end());
+ new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());
else
- for (int j = 0; j < SIZE(t)/2; j++)
- new_t.push_back(t[j] == t[j + SIZE(t)/2] ? t[j] : RTLIL::Sx);
+ for (int j = 0; j < GetSize(t)/2; j++)
+ new_t.push_back(t[j] == t[j + GetSize(t)/2] ? t[j] : RTLIL::Sx);
t.swap(new_t);
}
- log_assert(SIZE(t) == 1);
+ log_assert(GetSize(t) == 1);
return t;
}
@@ -360,6 +385,9 @@ struct CellTypes
}
};
+// initialized by yosys_setup()
+extern CellTypes yosys_celltypes;
+
YOSYS_NAMESPACE_END
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-05 17:36:53 +0000