1 files changed, 31 insertions, 17 deletions

diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index 9d88ac027..e7e4eab6e 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -49,9 +49,9 @@ struct TimingInfo
 
 	struct ModuleTiming
 	{
-		RTLIL::IdString type;
 		dict<BitBit, int> comb;
-		dict<NameBit, int> arrival, required;
+		dict<NameBit, std::pair<int,NameBit>> arrival, required;
+		bool has_inputs;
 	};
 
 	dict<RTLIL::IdString, ModuleTiming> data;
@@ -120,11 +120,10 @@ struct TimingInfo
 				}
 			}
 			else if (cell->type == ID($specify3)) {
-				auto src = cell->getPort(ID::SRC);
+				auto src = cell->getPort(ID::SRC).as_bit();
 				auto dst = cell->getPort(ID::DST);
-				for (const auto &c : src.chunks())
-					if (!c.wire->port_input)
-						log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
+				if (!src.wire || !src.wire->port_input)
+					log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
 				for (const auto &c : dst.chunks())
 					if (!c.wire->port_output)
 						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
@@ -136,34 +135,49 @@ struct TimingInfo
 					max = 0;
 				}
 				for (const auto &d : dst) {
-					auto &v = t.arrival[NameBit(d)];
-					v = std::max(v, max);
+					auto r = t.arrival.insert(NameBit(d));
+					auto &v = r.first->second;
+					if (r.second || v.first < max) {
+						v.first = max;
+						v.second = NameBit(src);
+					}
 				}
 			}
 			else if (cell->type == ID($specrule)) {
-				auto type = cell->getParam(ID::TYPE).decode_string();
-				if (type != "$setup" && type != "$setuphold")
+				IdString type = cell->getParam(ID::TYPE).decode_string();
+				if (type != ID($setup) && type != ID($setuphold))
 					continue;
 				auto src = cell->getPort(ID::SRC);
-				auto dst = cell->getPort(ID::DST);
+				auto dst = cell->getPort(ID::DST).as_bit();
 				for (const auto &c : src.chunks())
-					if (!c.wire->port_input)
+					if (!c.wire || !c.wire->port_input)
 						log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
-				for (const auto &c : dst.chunks())
-					if (!c.wire->port_input)
-						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
+				if (!dst.wire || !dst.wire->port_input)
+					log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
 				int max = cell->getParam(ID::T_LIMIT_MAX).as_int();
 				if (max < 0) {
 					log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
 					max = 0;
 				}
 				for (const auto &s : src) {
-					auto &v = t.required[NameBit(s)];
-					v = std::max(v, max);
+					auto r = t.required.insert(NameBit(s));
+					auto &v = r.first->second;
+					if (r.second || v.first < max) {
+						v.first = max;
+						v.second = NameBit(dst);
+					}
 				}
 			}
 		}
 
+		for (auto port_name : module->ports) {
+			auto wire = module->wire(port_name);
+			if (wire->port_input) {
+				t.has_inputs = true;
+				break;
+			}
+		}
+
 		return t;
 	}