diff options
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/celltypes.h | 2 | ||||
| -rw-r--r-- | kernel/log.cc | 7 | ||||
| -rw-r--r-- | kernel/log.h | 1 | ||||
| -rw-r--r-- | kernel/rtlil.cc | 6 | ||||
| -rw-r--r-- | kernel/satgen.h | 31 |
5 files changed, 38 insertions, 9 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 1eea0530c..9eb1523e9 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -118,6 +118,8 @@ struct CellTypes setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true); setup_type("$predict", {A, EN}, pool<RTLIL::IdString>(), true); setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true); + setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true); + setup_type("$aconst", pool<RTLIL::IdString>(), {Y}, true); setup_type("$equiv", {A, B}, {Y}, true); } diff --git a/kernel/log.cc b/kernel/log.cc index fe84184a5..12dc453dc 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -427,6 +427,13 @@ const char *log_id(RTLIL::IdString str) return p+1; } +void log_module(RTLIL::Module *module, std::string indent) +{ + std::stringstream buf; + ILANG_BACKEND::dump_module(buf, indent, module, module->design, false); + log("%s", buf.str().c_str()); +} + void log_cell(RTLIL::Cell *cell, std::string indent) { std::stringstream buf; diff --git a/kernel/log.h b/kernel/log.h index 33e624dcb..f830655c1 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -85,6 +85,7 @@ template<typename T> static inline const char *log_id(T *obj) { return log_id(obj->name); } +void log_module(RTLIL::Module *module, std::string indent = ""); void log_cell(RTLIL::Cell *cell, std::string indent = ""); #ifndef NDEBUG diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2e5157e85..ad90965fb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1030,6 +1030,12 @@ namespace { return; } + if (cell->type.in("$aconst", "$anyconst")) { + port("\\Y", param("\\WIDTH")); + check_expected(); + return; + } + if (cell->type == "$equiv") { port("\\A", 1); port("\\B", 1); diff --git a/kernel/satgen.h b/kernel/satgen.h index 31b7a3e5a..0a65b490c 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -69,7 +69,6 @@ struct SatGen SigPool initial_state; std::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en; std::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en; - std::map<std::string, RTLIL::SigSpec> predict_a, predict_en; std::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals; std::map<std::pair<std::string, int>, bool> initstates; bool ignore_div_by_zero; @@ -1320,6 +1319,28 @@ struct SatGen return true; } + if (cell->type == "$anyconst") + { + if (timestep < 2) + return true; + + std::vector<int> d = importDefSigSpec(cell->getPort("\\Y"), timestep-1); + std::vector<int> q = importDefSigSpec(cell->getPort("\\Y"), timestep); + + std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q; + ez->assume(ez->vec_eq(d, qq)); + + if (model_undef) + { + std::vector<int> undef_d = importUndefSigSpec(cell->getPort("\\D"), timestep-1); + std::vector<int> undef_q = importUndefSigSpec(cell->getPort("\\Q"), timestep); + + ez->assume(ez->vec_eq(undef_d, undef_q)); + undefGating(q, qq, undef_q); + } + return true; + } + if (cell->type == "$_BUF_" || cell->type == "$equiv") { std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep); @@ -1374,14 +1395,6 @@ struct SatGen return true; } - if (cell->type == "$predict") - { - std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - predict_a[pf].append((*sigmap)(cell->getPort("\\A"))); - predict_en[pf].append((*sigmap)(cell->getPort("\\EN"))); - return true; - } - // Unsupported internal cell types: $pow $lut // .. and all sequential cells except $dff and $_DFF_[NP]_ return false; |