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Diffstat (limited to 'manual/APPNOTE_012_Verilog_to_BTOR.tex')
| -rw-r--r-- | manual/APPNOTE_012_Verilog_to_BTOR.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/APPNOTE_012_Verilog_to_BTOR.tex b/manual/APPNOTE_012_Verilog_to_BTOR.tex index 67f15bc26..245a6b0b8 100644 --- a/manual/APPNOTE_012_Verilog_to_BTOR.tex +++ b/manual/APPNOTE_012_Verilog_to_BTOR.tex @@ -89,7 +89,7 @@ This Application Note is based on GIT Rev. {\tt 082550f} from We assume that the Verilog design is synthesizable and we also assume that the design does not have multi-dimensional memories. As BTOR implicitly initializes registers to zero value and memories stay -uninitilized, we assume that the Verilog design does +uninitialized, we assume that the Verilog design does not contain initial blocks. For more details about the BTOR format, please refer to~\cite{btor}. |