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Diffstat (limited to 'manual/CHAPTER_Overview.tex')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 645acd2d4..032c0f8c3 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -238,7 +238,7 @@ An RTLIL::Wire object has the following properties: \end{itemize} As with modules, the attributes can be Verilog attributes imported by the -Verilog frontend or attributes assigned by passees. +Verilog frontend or attributes assigned by passes. In Yosys, busses (signal vectors) are represented using a single wire object with a width > 1. So Yosys does not convert signal vectors to individual signals. @@ -412,7 +412,7 @@ Some passes refuse to operate on modules that still contain RTLIL::Process objec presence of these objects in a module increases the complexity. Therefore the passes to translate processes to a netlist of cells are usually called early in a synthesis script. The {\tt proc} pass calls a series of other passes that together perform this conversion in a way that is suitable -for most synthesis taks. +for most synthesis tasks. \subsection{RTLIL::Memory} |