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diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex index 21c5cdecc..471516b40 100644 --- a/manual/PRESENTATION_ExAdv.tex +++ b/manual/PRESENTATION_ExAdv.tex @@ -87,21 +87,21 @@ cd .. # switch back to design \end{lstlisting} \bigskip -Note: Most synthesis script never switch to module context. But it is a very powerful +Note: Most synthesis scripts never switch to module context. But it is a very powerful tool for interactive design investigation. \end{frame} \subsubsection{Selecting by object property or type} \begin{frame}[fragile]{\subsubsecname} -Special pattern can be used to select by object property or type. For example: +Special patterns can be used to select by object property or type. For example: \bigskip \begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] select w:reg_* # select all wires whose names start with reg_ select a:foobar # select all objects with the attribute foobar set select a:foobar=42 # select all objects with the attribute foobar set to 42 -select A:blabla # select all module with the attribute blabla set +select A:blabla # select all modules with the attribute blabla set select foo/t:$add # select all $add cells from the module foo \end{lstlisting} @@ -113,8 +113,8 @@ reference to the {\tt select} command. \subsubsection{Combining selection} \begin{frame}[fragile]{\subsubsecname} -When more than one selection expression is used in one statement they are -pushed on a stack. At the final elements on the stack are combined into a union: +When more than one selection expression is used in one statement, then they are +pushed on a stack. The final elements on the stack are combined into a union: \medskip \begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] @@ -169,8 +169,8 @@ See {\tt help select} for full documentation of this expressions. \subsubsection{Incremental selection} \begin{frame}[fragile]{\subsubsecname} -Sometime a selection can most easily described by a series of add/delete operations. -For the commands {\tt select -add} and {\tt select -del} add or remove objects +Sometimes a selection can most easily be described by a series of add/delete operations. +The commands {\tt select -add} and {\tt select -del} respectively add or remove objects from the current selection instead of overwriting it. \medskip @@ -223,11 +223,11 @@ show -color red @cone_ab -color magenta @cone_a -color blue @cone_b \begin{frame}[fragile]{\subsubsecname{} -- Example} \begin{columns} \column[t]{4cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/select_01.v} +\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/select.v} \column[t]{7cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExAdv/select_01.ys} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExAdv/select.ys} \end{columns} -\hfil\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/select_01.pdf} +\hfil\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/select.pdf} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -239,10 +239,233 @@ show -color red @cone_ab -color magenta @cone_a -color blue @cone_b \subsectionpagesuffix \end{frame} -\subsubsection{TBD} +\subsubsection{Introduction to techmap} \begin{frame}{\subsubsecname} -TBD +\begin{itemize} +\item +The {\tt techmap} command replaces cells in the design with implementations given +as verilog code (called ``map files''). It can replace Yosys' internal cell +types (such as {\tt \$or}) as well as user-defined cell types. +\medskip\item +Verilog parameters are used extensively to customize the internal cell types. +\medskip\item +Additional special parameters are used by techmap to communicate meta-data to the +map files. +\medskip\item +Special wires are used to instruct techmap how to handle a module in the map file. +\medskip\item +Generate blocks and recursion are powerful tools for writing map files. +\end{itemize} +\end{frame} + +\begin{frame}[t]{\subsubsecname{} -- Example 1/2} +\vskip-0.2cm +To map the Verilog OR-reduction operator to 3-input OR gates: +\vskip-0.2cm +\begin{columns} +\column[t]{0.35\linewidth} +\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=24]{PRESENTATION_ExAdv/red_or3x1_map.v} +\column[t]{0.65\linewidth} +\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=25]{PRESENTATION_ExAdv/red_or3x1_map.v} +\end{columns} +\end{frame} + +\begin{frame}[t]{\subsubsecname{} -- Example 2/2} +\vbox to 0cm{ +\hfil\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/red_or3x1.pdf} +\vss +} +\begin{columns} +\column[t]{6cm} +\column[t]{4cm} +\vskip-0.6cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, firstline=4, lastline=4, frame=single]{PRESENTATION_ExAdv/red_or3x1_test.ys} +\vskip-0.2cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/red_or3x1_test.v} +\end{columns} +\end{frame} + +\subsubsection{Conditional techmap} + +\begin{frame}{\subsubsecname} +\begin{itemize} +\item In some cases only cells with certain properties should be substituted. +\medskip +\item The special wire {\tt \_TECHMAP\_FAIL\_} can be used to disable a module +in the map file for a certain set of parameters. +\medskip +\item The wire {\tt \_TECHMAP\_FAIL\_} must be set to a constant value. If it +is non-zero then the module is disabled for this set of parameters. +\medskip +\item Example use-cases: +\begin{itemize} +\item coarse-grain cell types that only operate on certain bit widths +\item memory resources for different memory geometries (width, depth, ports, etc.) +\end{itemize} +\end{itemize} +\end{frame} + +\begin{frame}[t]{\subsubsecname{} -- Example} +\vbox to 0cm{ +\vskip-0.5cm +\hfill\includegraphics[width=6cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/sym_mul.pdf} +\vss +} +\vskip-0.5cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/sym_mul_map.v} +\begin{columns} +\column[t]{6cm} +\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/sym_mul_test.v} +\column[t]{4cm} +\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=4]{PRESENTATION_ExAdv/sym_mul_test.ys} +\end{columns} +\end{frame} + +\subsubsection{Scripting in map modules} + +\begin{frame}{\subsubsecname} +\begin{itemize} +\item The special wires {\tt \_TECHMAP\_DO\_*} can be used to run Yosys scripts +in the context of the replacement module. +\medskip +\item The wire that comes first in alphabetical oder is interpreted as string (must +be connected to constants) that is executed as script. Then the wire is removed. Repeat. +\medskip +\item You can even call techmap recursively! +\medskip +\item Example use-cases: +\begin{itemize} +\item Using always blocks in map module: call {\tt proc} +\item Perform expensive optimizations (such as {\tt freduce}) on cells where +this is known to work well. +\item Interacting with custom commands. +\end{itemize} +\end{itemize} + +\scriptsize +PROTIP: Commands such as {\tt shell}, {\tt show -pause}, and {\tt dump} can be use +in the {\tt \_TECHMAP\_DO\_*} scripts for debugging map modules. +\end{frame} + +\begin{frame}[t]{\subsubsecname{} -- Example} +\vbox to 0cm{ +\vskip4.2cm +\hskip0.5cm\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mymul.pdf} +\vss +} +\vskip-0.6cm +\begin{columns} +\column[t]{6cm} +\vskip-0.6cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mymul_map.v} +\column[t]{4.2cm} +\vskip-0.6cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mymul_test.v} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mymul_test.ys} +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, frame=single, language=ys, firstline=7, lastline=12]{PRESENTATION_ExAdv/mymul_test.ys} +\end{columns} +\end{frame} + +\subsubsection{Handling constant inputs} + +\begin{frame}{\subsubsecname} +\begin{itemize} +\item The special parameters {\tt \_TECHMAP\_CONSTMSK\_\it <port-name>\tt \_} and +{\tt \_TECHMAP\_CONSTVAL\_\it <port-name>\tt \_} can be used to handle constant +input values to cells. +\medskip +\item The former contains 1-bits for all constant input bits on the port. +\medskip +\item The latter contains the constant bits or undef (x) for non-constant bits. +\medskip +\item Example use-cases: +\begin{itemize} +\item Converting arithmetic (for example multiply to shift) +\item Identify constant addresses or enable bits in memory interfaces. +\end{itemize} +\end{itemize} +\end{frame} + +\begin{frame}[t]{\subsubsecname{} -- Example} +\vbox to 0cm{ +\vskip5.2cm +\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mulshift.pdf} +\vss +} +\vskip-0.6cm +\begin{columns} +\column[t]{6cm} +\vskip-0.4cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mulshift_map.v} +\column[t]{4.2cm} +\vskip-0.6cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mulshift_test.v} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mulshift_test.ys} +\end{columns} +\end{frame} + +\subsubsection{Handling shorted inputs} + +\begin{frame}{\subsubsecname} +\begin{itemize} +\item The special parameters {\tt \_TECHMAP\_BITS\_CONNMAP\_} and +{\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} can be used to handle shorted inputs. +\medskip +\item Each bit of the port correlates to an {\tt \_TECHMAP\_BITS\_CONNMAP\_} bits wide +number in {\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_}. +\medskip +\item Each unique signal bit is assigned its own number. Identical fields in the {\tt +\_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} parameters mean shorted signal bits. +\medskip +\item The numbers 0-3 are reserved for {\tt 0}, {\tt 1}, {\tt x}, and {\tt z} respectively. +\medskip +\item Example use-cases: +\begin{itemize} +\item Detecting shared clock or control signals in memory interfaces. +\item In some cases this can be used for for optimization. +\end{itemize} +\end{itemize} +\end{frame} + +\begin{frame}[t]{\subsubsecname{} -- Example} +\vbox to 0cm{ +\vskip4.5cm +\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/addshift.pdf} +\vss +} +\vskip-0.6cm +\begin{columns} +\column[t]{6cm} +\vskip-0.4cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/addshift_map.v} +\column[t]{4.2cm} +\vskip-0.6cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/addshift_test.v} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/addshift_test.ys} +\end{columns} +\end{frame} + +\subsubsection{Notes on using techmap} + +\begin{frame}{\subsubsecname} +\begin{itemize} +\item Don't use positional cell parameters in map modules. +\medskip +\item Don't try to implement basic logic optimization with techmap. \\ +{\small (So the OR-reduce using OR3X1 cells map was actually a bad example.)} +\medskip +\item You can use the {\tt \$\_\,\_}-prefix for internal cell types to avoid +collisions with the user-namespace. But always use two underscores or the +internal consistency checker will trigger on this cells. +\medskip +\item Techmap has two major use cases: +\begin{itemize} +\item Creating good logic-level representation of arithmetic functions. \\ +This also means using dedicated hardware resources such as half- and full-adder +cells in ASICS or dedicated carry logic in FPGAs. +\smallskip +\item Mapping of coarse-grain resources such as block memory or DSP cells. +\end{itemize} +\end{itemize} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -254,12 +477,328 @@ TBD \subsectionpagesuffix \end{frame} -\subsubsection{TBD} +\subsubsection{Intro to coarse-grain synthesis} + +\begin{frame}[fragile]{\subsubsecname} +In coarse-grain synthesis the target architecure has cells of the same +complexity or larger complexity than the internal RTL representation. + +For example: +\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog] + wire [15:0] a, b; + wire [31:0] c, y; + assign y = a * b + c; +\end{lstlisting} + +This circuit contains two cells in the RTL representation: one multiplier and +one adder. In some architectures this circuit can be implemented using +a single circuit element, for example an FPGA DSP core. Coarse grain synthesis +is this mapping of groups of circuit elements to larger components. + +\bigskip +Fine-grain synthesis would be matching the circuit elements to smaller +components, such as LUTs, gates, or half- and full-adders. +\end{frame} + +\subsubsection{The extract pass} + +\begin{frame}{\subsubsecname} +\begin{itemize} +\item Like the {\tt techmap} pass, the {\tt extract} pass is called with +a map file. It compares the circuits inside the modules of the map file +with the design and looks for sub-circuits in the design that match any +of the modules in the map file. +\bigskip +\item If a match is found, the {\tt extract} pass will replace the matching +subcircuit with an instance of the module from the map file. +\bigskip +\item In a way the {\tt extract} pass is the inverse of the techmap pass. +\end{itemize} +\end{frame} + +\begin{frame}[t, fragile]{\subsubsecname{} -- Example 1/2} +\vbox to 0cm{ +\vskip2cm +\begin{tikzpicture} + \node at (0,0) {\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00a.pdf}}; + \node at (3,-3) {\includegraphics[width=8cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00b.pdf}}; + \draw[yshift=0.2cm,thick,-latex] (1,-1) -- (2,-2); +\end{tikzpicture} +\vss} +\vskip-1.2cm +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test.v} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/macc_simple_xmap.v} +\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys] +read_verilog macc_simple_test.v +hierarchy -check -top test + +extract -map macc_simple_xmap.v;; +\end{lstlisting} +\end{columns} +\end{frame} + +\begin{frame}[fragile]{\subsubsecname{} -- Example 2/2} +\hfil\begin{tabular}{cc} +\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_01.v}}} & +\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_02.v}}} \\ +$\downarrow$ & $\downarrow$ \\ +\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01a.pdf}} & +\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02a.pdf}} \\ +$\downarrow$ & $\downarrow$ \\ +\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01b.pdf}} & +\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02b.pdf}} \\ +\end{tabular} +\end{frame} + +\subsubsection{The wrap-extract-unwrap method} \begin{frame}{\subsubsecname} -TBD +\scriptsize +Often a coarse-grain element has a constant bit-width, but can be used to +implement oprations with a smaller bit-width. For example, a 18x25-bit multiplier +can also be used to implement 16x20-bit multiplication. + +\bigskip +A way of mapping such elements in coarse grain synthesis is the wrap-extract-unwrap method: + +\begin{itemize} +\item {\bf wrap} \\ +Identify candidate-cells in the circuit and wrap them in a cell with a constant +wider bit-width using {\tt techmap}. The wrappers use the same parameters as the original cell, so +the information about the original width of the ports is preserved. \\ +Then use the {\tt connwrappers} command to connect up the bit-extended in- and +outputs of the wrapper cells. +\item {\bf extract} \\ +Now all operations are encoded using the same bit-width as the coarse grain element. The {\tt +extract} command can be used to replace circuits with cells of the target architecture. +\item {\bf unwrap} \\ +The remaining wrapper cell can be unwrapped using {\tt techmap}. +\end{itemize} + +\bigskip +The following sides detail an example that shows how to map MACC operations of +arbitrary size to MACC cells with a 18x25-bit multiplier and a 48-bit adder (such as +the Xilinx DSP48 cells). +\end{frame} + +\subsubsection{Example: DSP48\_MACC} + +\begin{frame}[t, fragile]{\subsubsecname{} -- 1/13} +Preconditioning: {\tt macc\_xilinx\_swap\_map.v} \\ +Make sure {\tt A} is the smaller port on all multipliers + +\begin{columns} +\column{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=15]{PRESENTATION_ExAdv/macc_xilinx_swap_map.v} +\column{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=16]{PRESENTATION_ExAdv/macc_xilinx_swap_map.v} +\end{columns} +\end{frame} + +\begin{frame}[t, fragile]{\subsubsecname{} -- 2/13} +Wrapping multipliers: {\tt macc\_xilinx\_wrap\_map.v} + +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=23]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=24, lastline=46]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v} +\end{columns} +\end{frame} + +\begin{frame}[t, fragile]{\subsubsecname{} -- 3/13} +Wrapping adders: {\tt macc\_xilinx\_wrap\_map.v} + +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=48, lastline=67]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=68, lastline=89]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v} +\end{columns} +\end{frame} + +\begin{frame}[t, fragile]{\subsubsecname{} -- 4/13} +Extract: {\tt macc\_xilinx\_xmap.v} + +\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=1, lastline=17]{PRESENTATION_ExAdv/macc_xilinx_xmap.v} + +.. simply use the same wrapping commands on this module as on the design to create a template for the {\tt extract} command. +\end{frame} + +\begin{frame}[t, fragile]{\subsubsecname{} -- 5/13} +Unwrapping multipliers: {\tt macc\_xilinx\_unwrap\_map.v} + +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=1, lastline=17]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=18, lastline=30]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v} +\end{columns} +\end{frame} + +\begin{frame}[t, fragile]{\subsubsecname{} -- 6/13} +Unwrapping adders: {\tt macc\_xilinx\_unwrap\_map.v} + +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=32, lastline=48]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=49, lastline=61]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v} +\end{columns} +\end{frame} + +\begin{frame}[fragile]{\subsubsecname{} -- 7/13} +\hfil\begin{tabular}{cc} +{\tt test1} & {\tt test2} \\ +\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=1, lastline=6, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} & +\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=8, lastline=13, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} \\ +$\downarrow$ & $\downarrow$ \\ +\end{tabular} +\vskip-0.5cm +\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] + read_verilog macc_xilinx_test.v + hierarchy -check +\end{lstlisting} +\vskip-0.5cm +\hfil\begin{tabular}{cc} +$\downarrow$ & $\downarrow$ \\ +\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} & +\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2a.pdf}} \\ +\end{tabular} +\end{frame} + +\begin{frame}[fragile]{\subsubsecname{} -- 8/13} +\hfil\begin{tabular}{cc} +{\tt test1} & {\tt test2} \\ +\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} & +\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2a.pdf}} \\ +$\downarrow$ & $\downarrow$ \\ +\end{tabular} +\vskip-0.2cm +\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] + techmap -map macc_xilinx_swap_map.v ;; +\end{lstlisting} +\vskip-0.2cm +\hfil\begin{tabular}{cc} +$\downarrow$ & $\downarrow$ \\ +\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1b.pdf}} & +\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2b.pdf}} \\ +\end{tabular} \end{frame} +\begin{frame}[t, fragile]{\subsubsecname{} -- 9/13} +Wrapping in {\tt test1}: +\begin{columns} +\column[t]{5cm} +\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1b.pdf}}\vss} +\column[t]{6cm} +\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +techmap -map macc_xilinx_wrap_map.v + +connwrappers -unsigned $__mul_wrapper \ + Y Y_WIDTH \ + -unsigned $__add_wrapper \ + Y Y_WIDTH ;; +\end{lstlisting} +\end{columns} + +\vskip1cm +\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf} +\end{frame} + +\begin{frame}[t, fragile]{\subsubsecname{} -- 10/13} +Wrapping in {\tt test2}: +\begin{columns} +\column[t]{5cm} +\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2b.pdf}}\vss} +\column[t]{6cm} +\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +techmap -map macc_xilinx_wrap_map.v + +connwrappers -unsigned $__mul_wrapper \ + Y Y_WIDTH \ + -unsigned $__add_wrapper \ + Y Y_WIDTH ;; +\end{lstlisting} +\end{columns} + +\vskip1cm +\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf} +\end{frame} + +\begin{frame}[t, fragile]{\subsubsecname{} -- 11/13} +Extract in {\tt test1}: +\begin{columns} +\column[t]{4.5cm} +\vbox to 0cm{ +\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +design -push +read_verilog macc_xilinx_xmap.v +techmap -map macc_xilinx_swap_map.v +techmap -map macc_xilinx_wrap_map.v;; +design -save __macc_xilinx_xmap +design -pop +\end{lstlisting} +\vss} +\column[t]{5.5cm} +\vskip-1cm +\begin{lstlisting}[linewidth=5.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +extract -constports -ignore_parameters \ + -map %__macc_xilinx_xmap \ + -swap $__add_wrapper A,B ;; +\end{lstlisting} +\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf}}\vss} +\end{columns} + +\vskip2cm +\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1d.pdf} +\end{frame} + +\begin{frame}[t, fragile]{\subsubsecname{} -- 12/13} +Extract in {\tt test2}: +\begin{columns} +\column[t]{4.5cm} +\vbox to 0cm{ +\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +design -push +read_verilog macc_xilinx_xmap.v +techmap -map macc_xilinx_swap_map.v +techmap -map macc_xilinx_wrap_map.v;; +design -save __macc_xilinx_xmap +design -pop +\end{lstlisting} +\vss} +\column[t]{5.5cm} +\vskip-1cm +\begin{lstlisting}[linewidth=5.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +extract -constports -ignore_parameters \ + -map %__macc_xilinx_xmap \ + -swap $__add_wrapper A,B ;; +\end{lstlisting} +\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf}}\vss} +\end{columns} + +\vskip2cm +\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf} +\end{frame} + +\begin{frame}[t, fragile]{\subsubsecname{} -- 13/13} +Unwrap in {\tt test2}: + +\hfil\begin{tikzpicture} +\node at (0,0) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}}; +\node at (0,-4) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2e.pdf}}; +\node at (1,-1.7) {\begin{lstlisting}[linewidth=5.5cm, frame=single, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] +techmap -map macc_xilinx_unwrap_map.v ;; +\end{lstlisting}}; +\draw[-latex] (4,-0.7) .. controls (5,-1.7) .. (4,-2.7); +\end{tikzpicture} +\end{frame} + + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Automatic design changes} @@ -269,10 +808,67 @@ TBD \subsectionpagesuffix \end{frame} -\subsubsection{TBD} +\subsubsection{Changing the design from Yosys} \begin{frame}{\subsubsecname} -TBD +Yosys commands can be used to change the design in memory. Examples of this are: + +\begin{itemize} +\item {\bf Changes in design hierarchy} \\ +Commands such as {\tt flatten} and {\tt submod} can be used to change the design hierarchy, i.e. +flatten the hierarchy or moving parts of a module to a submodule. This has applications in synthesis +scripts as well as in reverse engineering and analysis. + +\item {\bf Behavioral changes} \\ +Commands such as {\tt techmap} can be used to make behavioral changes to the design, for example +changing asynchonous resets to synchronous resets. This has applications in design space exploration +(evaluation of various architectures for one circuit). +\end{itemize} +\end{frame} + +\subsubsection{Example: Async reset to sync reset} + +\begin{frame}[t, fragile]{\subsubsecname} +The following techmap map file replaces all positive-edge async reset flip-flops with +positive-edge sync reset flip-flops. The code is taken from the example Yosys script +for ASIC synthesis of the Amber ARMv2 CPU. + +\begin{columns} +\column[t]{6cm} +\vbox to 0cm{ +\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog] +(* techmap_celltype = "$adff" *) +module adff2dff (CLK, ARST, D, Q); + + parameter WIDTH = 1; + parameter CLK_POLARITY = 1; + parameter ARST_POLARITY = 1; + parameter ARST_VALUE = 0; + + input CLK, ARST; + input [WIDTH-1:0] D; + output reg [WIDTH-1:0] Q; + + wire [1023:0] _TECHMAP_DO_ = "proc"; + + wire _TECHMAP_FAIL_ = !CLK_POLARITY || !ARST_POLARITY; +\end{lstlisting} +\vss} +\column[t]{4cm} +\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog] +// ..continued.. + + + always @(posedge CLK) + if (ARST) + Q <= ARST_VALUE; + else + <= D; + +endmodule +\end{lstlisting} +\end{columns} + \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -281,10 +877,8 @@ TBD \begin{frame}{\subsecname} \begin{itemize} -\item TBD -\item TBD -\item TBD -\item TBD +\item A lot can be achived in Yosys just with the standard set of commands. +\item The commands {\tt techmap} and {\tt extract} can be used to prototype many complex synthesis tasks. \end{itemize} \bigskip |