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Diffstat (limited to 'manual/PRESENTATION_ExSyn.tex')
| -rw-r--r-- | manual/PRESENTATION_ExSyn.tex | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex index 35d0b8a78..803982295 100644 --- a/manual/PRESENTATION_ExSyn.tex +++ b/manual/PRESENTATION_ExSyn.tex @@ -12,7 +12,7 @@ \begin{frame}{\subsecname} \begin{itemize} \item Reading and elaborating the design -\item High-level synthesis and optimization +\item Higher-level synthesis and optimization \begin{itemize} \item Converting {\tt always}-blocks to logic and registers \item Perform coarse-grain optimizations (resource sharing, const folding, ...) @@ -21,7 +21,7 @@ \end{itemize} \item Convert remaining logic to bit-level logic functions \item Perform optimizations on bit-level logic functions -\item Map bit-level logic and register to gates from cell library +\item Map bit-level logic gates and registers to cell library \item Write results to output file \end{itemize} \end{frame} @@ -64,8 +64,8 @@ all needed variations of parametric modules. # hierarchy -# recommended form. fail if parts of the design hierarchy are missing. remove -# everything that is unreachable by the top module. mark the top module. +# recommended form. fails if parts of the design hierarchy are missing, removes +# everything that is unreachable from the top module, and marks the top module. # hierarchy -check -top top_module \end{lstlisting} @@ -223,7 +223,7 @@ The designs in {\tt yosys-bigsim} are a good playground for experimenting with the effects of calling {\tt opt} in various places of the flow. \bigskip -It generally is a good idea us call {\tt opt} before inherently expensive +It generally is a good idea to call {\tt opt} before inherently expensive commands such as {\tt sat} or {\tt freduce}, as the possible gain is much higher in this cases as the possible loss. @@ -253,7 +253,7 @@ memory_dff # into one multi-port memory cell. memory_collect -# this takes the multi-port memory cells and transforms it to address decoder +# this takes the multi-port memory cell and transforms it to address decoder # logic and registers. This step is skipped if "memory" is called with -nomap. memory_map \end{lstlisting} @@ -279,7 +279,7 @@ memory -nomap; techmap -map my_memory_map.v; memory_map \end{frame} \begin{frame}[t, fragile]{\subsecname{} -- Example 2/2} -\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -6cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss} +\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -5cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss} \vskip-1cm \begin{columns} \column[t]{5cm} @@ -303,11 +303,11 @@ fsm_detect # unless got option -nodetect fsm_extract fsm_opt -opt_clean +clean fsm_opt fsm_expand # if got option -expand -opt_clean # if got option -expand +clean # if got option -expand fsm_opt # if got option -expand fsm_recode # unless got option -norecode @@ -346,7 +346,7 @@ Finally the {\tt fsm\_map} command can be used to convert the (optimized) {\tt \subsection{The {\tt techmap} command} \begin{frame}[t]{\subsecname} -\vbox to 0cm{\includegraphics[width=12cm,trim=-18cm 0cm 0cm -34cm]{PRESENTATION_ExSyn/techmap_01.pdf}\vss} +\vbox to 0cm{\includegraphics[width=12cm,trim=-15cm 0cm 0cm -20cm]{PRESENTATION_ExSyn/techmap_01.pdf}\vss} \vskip-0.8cm The {\tt techmap} command replaces cells with implementations given as verilog source. For example implementing a 32 bit adder using 16 bit adders: @@ -366,8 +366,8 @@ When {\tt techmap} is used without a map file, it uses a built-in map file to map all RTL cell types to a generic library of built-in logic gates and registers. \bigskip -\begin{block}{The build-in logic gate types are:} -{\tt \$\_INV\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_} +\begin{block}{The built-in logic gate types are:} +{\tt \$\_NOT\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_} \end{block} \bigskip @@ -496,7 +496,7 @@ the next part (Section 3, ``Advanced Synthesis'') of this presentation.} \begin{itemize} \item Yosys provides commands for each phase of the synthesis. \item Each command solves a (more or less) simple problem. -\item Complex command are often only front-ends to simple commands. +\item Complex commands are often only front-ends to simple commands. \item {\tt proc; opt; memory; opt; fsm; opt; techmap; opt; abc;;} \end{itemize} |