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Diffstat (limited to 'manual/PRESENTATION_Prog.tex')
| -rw-r--r-- | manual/PRESENTATION_Prog.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex index 97ec76fe8..6b105a701 100644 --- a/manual/PRESENTATION_Prog.tex +++ b/manual/PRESENTATION_Prog.tex @@ -124,7 +124,7 @@ has been executed. \begin{frame}{\subsecname} The RTLIL data structures are simple structs utilizing {\tt pool<>} and -{\tt dict<>} containers (drop-in replacementments for {\tt +{\tt dict<>} containers (drop-in replacements for {\tt std::unordered\_set<>} and {\tt std::unordered\_map<>}). \bigskip @@ -413,7 +413,7 @@ When modifying existing modules, stick to the following DOs and DON'Ts: \item Use {\tt module->fixup\_ports()} after changing the {\tt port\_*} properties of wires. -\item You can safely remove cells or change the {\tt connetions} property of a cell, but be careful when +\item You can safely remove cells or change the {\tt connections} property of a cell, but be careful when changing the size of the {\tt SigSpec} connected to a cell port. \item Use the {\tt SigMap} helper class (see next slide) when you need a unique handle for each signal bit. |