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diff --git a/manual/presentation.tex b/manual/presentation.tex index bfd09a498..049980281 100644 --- a/manual/presentation.tex +++ b/manual/presentation.tex @@ -83,9 +83,27 @@ \titlepage \end{frame} -\setcounter{section}{-1} -\section{Outline} +\setcounter{section}{-2} + +\section{Abstract} +\begin{frame}{Abstract} +Yosys is the first full-featured open source software for Verilog HDL +synthesis. It supports most of Verilog-2005 and is well tested with +real-world designs from the ASIC and FPGA world. + +\bigskip +Learn how to use Yosys to create your own custom synthesis flows and discover +why open source HDL synthesis is important for researchers, hobbyists, +educators and engineers alike. +\bigskip +This presentation covers basic concepts of Yosys, creating simple synthesis +scripts, creating synthesis scripts for advanced applications, creating Yosys +scripts for non-synthesis applications (such as formal equivialence checking) +and writing extensions to Yosys using the C++ API. +\end{frame} + +\section{Outline} \begin{frame}{Outline} Yosys is an Open Source Verilog synthesis tool, and more. |