diff options
Diffstat (limited to 'passes/cmds/splice.cc')
| -rw-r--r-- | passes/cmds/splice.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 8856e21c9..f99090279 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -75,10 +75,10 @@ struct SpliceWorker RTLIL::SigSpec new_sig = sig; if (sig_a.size() != sig.size()) { - RTLIL::Cell *cell = module->addCell(NEW_ID, "$slice"); - cell->parameters["\\OFFSET"] = offset; - cell->parameters["\\A_WIDTH"] = sig_a.size(); - cell->parameters["\\Y_WIDTH"] = sig.size(); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice)); + cell->parameters[ID::OFFSET] = offset; + cell->parameters[ID::A_WIDTH] = sig_a.size(); + cell->parameters[ID::Y_WIDTH] = sig.size(); cell->setPort(ID::A, sig_a); cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size())); new_sig = cell->getPort(ID::Y); @@ -132,9 +132,9 @@ struct SpliceWorker RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front()); for (size_t i = 1; i < chunks.size(); i++) { RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]); - RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat"); - cell->parameters["\\A_WIDTH"] = new_sig.size(); - cell->parameters["\\B_WIDTH"] = sig2.size(); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat)); + cell->parameters[ID::A_WIDTH] = new_sig.size(); + cell->parameters[ID::B_WIDTH] = sig2.size(); cell->setPort(ID::A, new_sig); cell->setPort(ID::B, sig2); cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size())); |