diff options
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_export.cc | 4 | ||||
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_map.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_opt.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_recode.cc | 12 | ||||
| -rw-r--r-- | passes/fsm/fsmdata.h | 2 |
6 files changed, 12 insertions, 12 deletions
diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index dc9ec2b06..cc328ce34 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -60,8 +60,8 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st attr_it = cell->attributes.find("\\fsm_export"); if (!filename.empty()) { kiss_name.assign(filename); - } else if (attr_it != cell->attributes.end() && attr_it->second.str != "") { - kiss_name.assign(attr_it->second.str); + } else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") { + kiss_name.assign(attr_it->second.decode_string()); } else { kiss_name.assign(module->name); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index d077ef4a4..dc3a9ec09 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -376,7 +376,7 @@ struct FsmExtractPass : public Pass { std::vector<RTLIL::Wire*> wire_list; for (auto &wire_it : module->wires) - if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].str != "none") + if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].decode_string() != "none") if (design->selected(module, wire_it.second)) wire_list.push_back(wire_it.second); for (auto wire : wire_list) diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index b8edf420a..c30cf1fe7 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -168,7 +168,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) // create state register RTLIL::Wire *state_wire = new RTLIL::Wire; - state_wire->name = fsm_cell->parameters["\\NAME"].str; + state_wire->name = fsm_cell->parameters["\\NAME"].decode_string(); while (module->count_id(state_wire->name) > 0) state_wire->name += "_"; state_wire->width = fsm_data.state_bits; diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index ad8f3ff3b..242a505e9 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -42,7 +42,7 @@ struct FsmOpt if (!wire || wire->attributes.count("\\unused_bits") == 0) return false; - char *str = strdup(wire->attributes["\\unused_bits"].str.c_str()); + char *str = strdup(wire->attributes["\\unused_bits"].decode_string().c_str()); for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) { if (tok[0] && bit == atoi(tok)) return true; diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 99ee0eb53..5a4e091cf 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -28,12 +28,12 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f) { + std::string name = cell->parameters["\\NAME"].decode_string(); + fprintf(f, "set_fsm_state_vector {"); for (int i = fsm_data.state_bits-1; i >= 0; i--) - fprintf(f, " %s_reg[%d]", cell->parameters["\\NAME"].str[0] == '\\' ? - cell->parameters["\\NAME"].str.substr(1).c_str() : cell->parameters["\\NAME"].str.c_str(), i); - fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", - prefix, RTLIL::unescape_id(cell->parameters["\\NAME"].str).c_str(), + fprintf(f, " %s_reg[%d]", name[0] == '\\' ? name.substr(1).c_str() : name.c_str(), i); + fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", prefix, RTLIL::unescape_id(name).c_str(), prefix, RTLIL::unescape_id(module->name).c_str()); fprintf(f, "set_fsm_encoding {"); @@ -43,13 +43,13 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData & fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0'); } fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", - prefix, RTLIL::unescape_id(cell->parameters["\\NAME"].str).c_str(), + prefix, RTLIL::unescape_id(name).c_str(), prefix, RTLIL::unescape_id(module->name).c_str()); } static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, std::string default_encoding) { - std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").str : "auto"; + std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").decode_string() : "auto"; log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str()); if (encoding != "none" && encoding != "one-hot" && encoding != "binary") { diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index f43b25fe9..225f34a9d 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -133,7 +133,7 @@ struct FsmData { log("-------------------------------------\n"); log("\n"); - log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters["\\NAME"].str.c_str()); + log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters["\\NAME"].decode_string().c_str()); log("\n"); log(" Number of input signals: %3d\n", num_inputs); log(" Number of output signals: %3d\n", num_outputs); |