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Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 76b667b86..8c09d2eaa 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -118,13 +118,10 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell design->modules[mod->name] = mod; for (auto &decl : ports) { - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = decl.portname; - wire->width = portwidths.at(decl.portname); + RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname)); wire->port_id = decl.index; wire->port_input = decl.input; wire->port_output = decl.output; - mod->add(wire); } for (auto ¶ : parameters) |