1 files changed, 41 insertions, 41 deletions

diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index 49ec66792..9173c791b 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -31,53 +31,53 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 	log("Creating $memrd and $memwr for memory `%s' in module `%s':\n",
 			memory->name.c_str(), module->name.c_str());
 
-	RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string());
+	RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at(ID::MEMID).decode_string());
 
 	while (module->memories.count(mem_name) != 0)
 		mem_name = mem_name.str() + stringf("_%d", autoidx++);
 
 	RTLIL::Memory *mem = new RTLIL::Memory;
 	mem->name = mem_name;
-	mem->width = memory->parameters.at("\\WIDTH").as_int();
-	mem->start_offset = memory->parameters.at("\\OFFSET").as_int();
-	mem->size = memory->parameters.at("\\SIZE").as_int();
+	mem->width = memory->parameters.at(ID::WIDTH).as_int();
+	mem->start_offset = memory->parameters.at(ID::OFFSET).as_int();
+	mem->size = memory->parameters.at(ID::SIZE).as_int();
 	module->memories[mem_name] = mem;
 
-	int abits = memory->parameters.at("\\ABITS").as_int();
-	int num_rd_ports = memory->parameters.at("\\RD_PORTS").as_int();
-	int num_wr_ports = memory->parameters.at("\\WR_PORTS").as_int();
+	int abits = memory->parameters.at(ID::ABITS).as_int();
+	int num_rd_ports = memory->parameters.at(ID::RD_PORTS).as_int();
+	int num_wr_ports = memory->parameters.at(ID::WR_PORTS).as_int();
 
 	for (int i = 0; i < num_rd_ports; i++)
 	{
-		RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd");
-		cell->parameters["\\MEMID"] = mem_name.str();
-		cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
-		cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
-		cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
-		cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
-		cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const();
-		cell->setPort("\\CLK", memory->getPort("\\RD_CLK").extract(i, 1));
-		cell->setPort("\\EN", memory->getPort("\\RD_EN").extract(i, 1));
-		cell->setPort("\\ADDR", memory->getPort("\\RD_ADDR").extract(i*abits, abits));
-		cell->setPort("\\DATA", memory->getPort("\\RD_DATA").extract(i*mem->width, mem->width));
+		RTLIL::Cell *cell = module->addCell(NEW_ID, ID($memrd));
+		cell->parameters[ID::MEMID] = mem_name.str();
+		cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS);
+		cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH);
+		cell->parameters[ID::CLK_ENABLE] = RTLIL::SigSpec(memory->parameters.at(ID::RD_CLK_ENABLE)).extract(i, 1).as_const();
+		cell->parameters[ID::CLK_POLARITY] = RTLIL::SigSpec(memory->parameters.at(ID::RD_CLK_POLARITY)).extract(i, 1).as_const();
+		cell->parameters[ID::TRANSPARENT] = RTLIL::SigSpec(memory->parameters.at(ID::RD_TRANSPARENT)).extract(i, 1).as_const();
+		cell->setPort(ID::CLK, memory->getPort(ID::RD_CLK).extract(i, 1));
+		cell->setPort(ID::EN, memory->getPort(ID::RD_EN).extract(i, 1));
+		cell->setPort(ID::ADDR, memory->getPort(ID::RD_ADDR).extract(i*abits, abits));
+		cell->setPort(ID::DATA, memory->getPort(ID::RD_DATA).extract(i*mem->width, mem->width));
 	}
 
 	for (int i = 0; i < num_wr_ports; i++)
 	{
-		RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr");
-		cell->parameters["\\MEMID"] = mem_name.str();
-		cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
-		cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
-		cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
-		cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
-		cell->parameters["\\PRIORITY"] = i;
-		cell->setPort("\\CLK", memory->getPort("\\WR_CLK").extract(i, 1));
-		cell->setPort("\\EN", memory->getPort("\\WR_EN").extract(i*mem->width, mem->width));
-		cell->setPort("\\ADDR", memory->getPort("\\WR_ADDR").extract(i*abits, abits));
-		cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width));
+		RTLIL::Cell *cell = module->addCell(NEW_ID, ID($memwr));
+		cell->parameters[ID::MEMID] = mem_name.str();
+		cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS);
+		cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH);
+		cell->parameters[ID::CLK_ENABLE] = RTLIL::SigSpec(memory->parameters.at(ID::WR_CLK_ENABLE)).extract(i, 1).as_const();
+		cell->parameters[ID::CLK_POLARITY] = RTLIL::SigSpec(memory->parameters.at(ID::WR_CLK_POLARITY)).extract(i, 1).as_const();
+		cell->parameters[ID::PRIORITY] = i;
+		cell->setPort(ID::CLK, memory->getPort(ID::WR_CLK).extract(i, 1));
+		cell->setPort(ID::EN, memory->getPort(ID::WR_EN).extract(i*mem->width, mem->width));
+		cell->setPort(ID::ADDR, memory->getPort(ID::WR_ADDR).extract(i*abits, abits));
+		cell->setPort(ID::DATA, memory->getPort(ID::WR_DATA).extract(i*mem->width, mem->width));
 	}
 
-	Const initval = memory->parameters.at("\\INIT");
+	Const initval = memory->parameters.at(ID::INIT);
 	RTLIL::Cell *last_init_cell = nullptr;
 	SigSpec last_init_data;
 	int last_init_addr=0;
@@ -90,19 +90,19 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 		continue;
 	found_non_undef_initval:
 		if (last_init_cell && last_init_addr+1 == i/mem->width) {
-			last_init_cell->parameters["\\WORDS"] = last_init_cell->parameters["\\WORDS"].as_int() + 1;
+			last_init_cell->parameters[ID::WORDS] = last_init_cell->parameters[ID::WORDS].as_int() + 1;
 			last_init_data.append(val);
 			last_init_addr++;
 		} else {
 			if (last_init_cell)
-				last_init_cell->setPort("\\DATA", last_init_data);
-			RTLIL::Cell *cell = module->addCell(NEW_ID, "$meminit");
-			cell->parameters["\\MEMID"] = mem_name.str();
-			cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
-			cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
-			cell->parameters["\\WORDS"] = 1;
-			cell->parameters["\\PRIORITY"] = i/mem->width;
-			cell->setPort("\\ADDR", SigSpec(i/mem->width, abits));
+				last_init_cell->setPort(ID::DATA, last_init_data);
+			RTLIL::Cell *cell = module->addCell(NEW_ID, ID($meminit));
+			cell->parameters[ID::MEMID] = mem_name.str();
+			cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS);
+			cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH);
+			cell->parameters[ID::WORDS] = 1;
+			cell->parameters[ID::PRIORITY] = i/mem->width;
+			cell->setPort(ID::ADDR, SigSpec(i/mem->width, abits));
 			last_init_cell = cell;
 			last_init_addr = i/mem->width;
 			last_init_data = val;
@@ -110,7 +110,7 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 	}
 
 	if (last_init_cell)
-		last_init_cell->setPort("\\DATA", last_init_data);
+		last_init_cell->setPort(ID::DATA, last_init_data);
 
 	module->remove(memory);
 }
@@ -119,7 +119,7 @@ void handle_module(RTLIL::Design *design, RTLIL::Module *module)
 {
 	std::vector<RTLIL::IdString> memcells;
 	for (auto &cell_it : module->cells_)
-		if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second))
+		if (cell_it.second->type == ID($mem) && design->selected(module, cell_it.second))
 			memcells.push_back(cell_it.first);
 	for (auto &it : memcells)
 		handle_memory(module, module->cells_.at(it));