4 files changed, 5 insertions, 5 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index b387e0381..b9ff5d302 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -262,7 +262,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 	}
 
 
-	pool<RTLIL::Wire*, hash_obj_ops> del_wires;
+	pool<RTLIL::Wire*> del_wires;
 
 	int del_wires_count = 0;
 	for (auto wire : maybe_del_wires)
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index f78ea6cc3..7f800bde9 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -199,7 +199,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 	dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
 
 	TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
-	dict<RTLIL::Cell*, std::set<RTLIL::SigBit>, hash_obj_ops> cell_to_inbit;
+	dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
 	dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
 
 	for (auto cell : module->cells())
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 91bfd58ab..c581b749e 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -41,7 +41,7 @@ struct OptShareWorker
 	CellTypes ct;
 	int total_count;
 #ifdef USE_CELL_HASH_CACHE
-	dict<const RTLIL::Cell*, std::string, hash_obj_ops> cell_hash_cache;
+	dict<const RTLIL::Cell*, std::string> cell_hash_cache;
 #endif
 
 #ifdef USE_CELL_HASH_CACHE
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 41a4a6908..0d1a54d97 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -731,7 +731,7 @@ struct ShareWorker
 			return forbidden_controls_cache.at(cell);
 
 		pool<ModWalker::PortBit> pbits;
-		pool<RTLIL::Cell*, hash_obj_ops> consumer_cells;
+		pool<RTLIL::Cell*> consumer_cells;
 
 		modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]);
 
@@ -803,7 +803,7 @@ struct ShareWorker
 			return activation_patterns_cache.at(cell);
 
 		const pool<RTLIL::SigBit> &cell_out_bits = modwalker.cell_outputs[cell];
-		pool<RTLIL::Cell*, hash_obj_ops> driven_cells, driven_data_muxes;
+		pool<RTLIL::Cell*> driven_cells, driven_data_muxes;
 
 		for (auto &bit : cell_out_bits)
 		{