aboutsummaryrefslogtreecommitdiffstats
path: root/passes/pmgen/xilinx_dsp.pmg
diff options
context:
space:
mode:
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
-rw-r--r--passes/pmgen/xilinx_dsp.pmg20
1 files changed, 10 insertions, 10 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 7a175123e..a97ab4dd5 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -1,7 +1,7 @@
pattern xilinx_dsp
state <SigBit> clock
-state <SigSpec> P_used
+state <SigSpec> sigPused
match dsp
select dsp->type.in(\DSP48E1)
@@ -43,23 +43,23 @@ endcode
// Extract the bits of P that actually have a consumer
// (as opposed to being a sign extension)
-code P_used
+code sigPused
SigSpec P = port(dsp, \P);
int i;
for (i = GetSize(P); i > 0; i--)
if (nusers(P[i-1]) > 1)
break;
- P_used = P.extract(0, i).remove_const();
+ sigPused = P.extract(0, i).remove_const();
endcode
match ffP
- if !P_used.empty()
+ if !sigPused.empty()
select ffP->type.in($dff, $dffe)
select nusers(port(ffP, \D)) == 2
// DSP48E1 does not support clock inversion
select param(ffP, \CLK_POLARITY).as_bool()
- filter param(ffP, \WIDTH).as_int() >= GetSize(P_used)
- filter includes(port(ffP, \D).to_sigbit_set(), P_used.to_sigbit_set())
+ filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
+ filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set())
optional
endmatch
@@ -68,12 +68,12 @@ endmatch
// since that would lose information helpful for
// efficient wide-mux inference
match muxP
- if !P_used.empty() && !ffP
+ if !sigPused.empty() && !ffP
select muxP->type.in($mux)
select nusers(port(muxP, \B)) == 2
select port(muxP, \A).is_fully_undef()
- filter param(muxP, \WIDTH).as_int() >= GetSize(P_used)
- filter includes(port(muxP, \B).to_sigbit_set(), P_used.to_sigbit_set())
+ filter param(muxP, \WIDTH).as_int() >= GetSize(sigPused)
+ filter includes(port(muxP, \B).to_sigbit_set(), sigPused.to_sigbit_set())
optional
endmatch
@@ -83,7 +83,7 @@ match ffY
select nusers(port(ffY, \D)) == 2
// DSP48E1 does not support clock inversion
select param(ffY, \CLK_POLARITY).as_bool()
- filter param(ffY, \WIDTH).as_int() >= GetSize(P_used)
+ filter param(ffY, \WIDTH).as_int() >= GetSize(sigPused)
filter includes(port(ffY, \D).to_sigbit_set(), port(muxP, \Y).to_sigbit_set())
endmatch