diff options
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 67d0981f4..2aa19b348 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -548,6 +548,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"]; if (mapped_mod == NULL) log_error("ABC output file does not contain a module `netlist'.\n"); + Pass::call(mapped_design, "clean"); pool<RTLIL::SigBit> output_bits; for (auto &it : mapped_mod->wires_) { |