1 files changed, 0 insertions, 35 deletions

diff --git a/passes/techmap/abc9_map.cc b/passes/techmap/abc9_map.cc
index 83f90a762..6b9d0afff 100644
--- a/passes/techmap/abc9_map.cc
+++ b/passes/techmap/abc9_map.cc
@@ -960,48 +960,13 @@ struct Abc9MapPass : public Pass {
 			}
 		}
 
-		SigMap assign_map;
-		CellTypes ct(design);
 		for (auto module : design->selected_modules())
 		{
 			if (module->processes.size() > 0)
 				log_error("Module '%s' has processes!\n", log_id(module));
 
-			assign_map.set(module);
-
-			typedef SigSpec clkdomain_t;
-			dict<clkdomain_t, int> clk_to_mergeability;
-
 			const std::vector<RTLIL::Cell*> all_cells = module->selected_cells();
 
-			for (auto cell : all_cells) {
-				auto inst_module = design->module(cell->type);
-				if (!inst_module || !inst_module->attributes.count("\\abc9_flop")
-						|| cell->get_bool_attribute("\\abc9_keep"))
-					continue;
-
-				Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str()));
-				if (abc9_clock_wire == NULL)
-					log_error("'%s$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-				SigSpec abc9_clock = assign_map(abc9_clock_wire);
-
-				clkdomain_t key(abc9_clock);
-
-				auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
-				auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
-				log_assert(r2.second);
-
-				Wire *abc9_init_wire = module->wire(stringf("%s.$abc9_init", cell->name.c_str()));
-				if (abc9_init_wire == NULL)
-				    log_error("'%s.$abc9_init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-				log_assert(GetSize(abc9_init_wire) == 1);
-				SigSpec abc9_init = assign_map(abc9_init_wire);
-				if (!abc9_init.is_fully_const())
-				    log_error("'%s.$abc9_init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-				r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
-				log_assert(r2.second);
-			}
-
 			design->selected_active_module = module->name.str();
 			abc9_module(design, module, script_file, exe_file, lut_costs,
 					delay_target, lutin_shared, fast_mode, all_cells, show_tempdir,