diff options
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc.cc | 16 | ||||
| -rw-r--r-- | passes/techmap/abc9.cc | 8 | ||||
| -rw-r--r-- | passes/techmap/aigmap.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/deminout.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/dff2dffe.cc | 4 | ||||
| -rw-r--r-- | passes/techmap/simplemap.cc | 2 |
6 files changed, 17 insertions, 17 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 41a05c619..73f63a4e1 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -166,7 +166,7 @@ void mark_port(RTLIL::SigSpec sig) void extract_cell(RTLIL::Cell *cell, bool keepff) { - if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") + if (cell->type.in("$_DFF_N_", "$_DFF_P_")) { if (clk_polarity != (cell->type == "$_DFF_P_")) return; @@ -177,11 +177,11 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) goto matching_dff; } - if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_") + if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_")) { - if (clk_polarity != (cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")) + if (clk_polarity != cell->type.in("$_DFFE_PN_", "$_DFFE_PP_")) return; - if (en_polarity != (cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_")) + if (en_polarity != cell->type.in("$_DFFE_NP_", "$_DFFE_PP_")) return; if (clk_sig != assign_map(cell->getPort("\\C"))) return; @@ -1824,15 +1824,15 @@ struct AbcPass : public Pass { } } - if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") + if (cell->type.in("$_DFF_N_", "$_DFF_P_")) { key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec()); } else - if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_") + if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_" "$_DFFE_PN_", "$_DFFE_PP_")) { - bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"; - bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"; + bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"); + bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"); key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E"))); } else diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 658bb1225..34919cf07 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1137,15 +1137,15 @@ struct Abc9Pass : public Pass { } } - if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") + if (cell->type.in("$_DFF_N_", "$_DFF_P_")) { key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec()); } else - if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_") + if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_")) { - bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"; - bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"; + bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"); + bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"); key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E"))); } else diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc index 35df2ff79..2423676cb 100644 --- a/passes/techmap/aigmap.cc +++ b/passes/techmap/aigmap.cc @@ -66,7 +66,7 @@ struct AigmapPass : public Pass { { Aig aig(cell); - if (cell->type == "$_AND_" || cell->type == "$_NOT_") + if (cell->type.in("$_AND_", "$_NOT_")) aig.name.clear(); if (nand_mode && cell->type == "$_NAND_") diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index 47d0ff416..142d12bdc 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -85,7 +85,7 @@ struct DeminoutPass : public Pass { if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_", "$tribuf")) { - bool tribuf = (cell->type == "$_TBUF_" || cell->type == "$tribuf"); + bool tribuf = cell->type.in("$_TBUF_", "$tribuf"); if (!tribuf) { for (auto &c : cell->connections()) { diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 7e1040963..44bc14628 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -52,13 +52,13 @@ struct Dff2dffeWorker } for (auto cell : module->cells()) { - if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") { + if (cell->type.in("$mux", "$pmux", "$_MUX_")) { RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y")); for (int i = 0; i < GetSize(sig_y); i++) bit2mux[sig_y[i]] = cell_int_t(cell, i); } if (direct_dict.empty()) { - if (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") + if (cell->type.in("$dff", "$_DFF_N_", "$_DFF_P_")) dff_cells.push_back(cell); } else { if (direct_dict.count(cell->type)) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index f3da80c66..6c70ffd4f 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -245,7 +245,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool(); - bool is_ne = cell->type == "$ne" || cell->type == "$nex"; + bool is_ne = cell->type.in("$ne", "$nex"); RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); |