3 files changed, 15 insertions, 50 deletions

diff --git a/passes/techmap/dffunmap.cc b/passes/techmap/dffunmap.cc
index 583185e75..7312015f1 100644
--- a/passes/techmap/dffunmap.cc
+++ b/passes/techmap/dffunmap.cc
@@ -86,19 +86,18 @@ struct DffunmapPass : public Pass {
 				if (ce_only) {
 					if (!ff.has_ce)
 						continue;
-					ff.unmap_ce(mod);
+					ff.unmap_ce();
 				} else if (srst_only) {
 					if (!ff.has_srst)
 						continue;
-					ff.unmap_srst(mod);
+					ff.unmap_srst();
 				} else {
 					if (!ff.has_ce && !ff.has_srst)
 						continue;
-					ff.unmap_ce_srst(mod);
+					ff.unmap_ce_srst();
 				}
 
-				mod->remove(cell);
-				ff.emit(mod, name);
+				ff.emit();
 			}
 		}
 	}
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 04d7ec874..68f44cf6d 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -368,13 +368,13 @@ void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
 	module->connect(RTLIL::SigSig(sig_y, sig_ab));
 }
 
-void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell)
+void simplemap_ff(RTLIL::Module *, RTLIL::Cell *cell)
 {
 	FfData ff(nullptr, cell);
 	for (int i = 0; i < ff.width; i++) {
 		FfData fff = ff.slice({i});
 		fff.is_fine = true;
-		fff.emit(module, NEW_ID);
+		fff.emit();
 	}
 }
 
diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc
index 8fcc47570..cc208c516 100644
--- a/passes/techmap/zinit.cc
+++ b/passes/techmap/zinit.cc
@@ -25,14 +25,6 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-State invert(State s) {
-	switch (s) {
-		case State::S0: return State::S1;
-		case State::S1: return State::S0;
-		default: return s;
-	}
-}
-
 struct ZinitPass : public Pass {
 	ZinitPass() : Pass("zinit", "add inverters so all FF are zero-initialized") { }
 	void help() override
@@ -75,45 +67,19 @@ struct ZinitPass : public Pass {
 					continue;
 
 				FfData ff(&initvals, cell);
-				if (!ff.width)
-					continue;
-
-				// Supporting those would require a new cell type where S has priority over R.
-				if (ff.has_sr)
-					continue;
-
-				Wire *new_q = module->addWire(NEW_ID, ff.width);
 
 				log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type),
 						log_signal(ff.sig_q), log_signal(ff.val_init));
 
-				IdString name = cell->name;
-				module->remove(cell);
-				initvals.remove_init(ff.sig_q);
-
-				for (int i = 0; i < ff.width; i++)
-					if (ff.val_init[i] == State::S1)
-					{
-						if (ff.has_clk || ff.has_gclk)
-							ff.sig_d[i] = module->NotGate(NEW_ID, ff.sig_d[i]);
-						if (ff.has_aload)
-							ff.sig_ad[i] = module->NotGate(NEW_ID, ff.sig_ad[i]);
-						if (ff.has_arst)
-							ff.val_arst[i] = invert(ff.val_arst[i]);
-						if (ff.has_srst)
-							ff.val_srst[i] = invert(ff.val_srst[i]);
-						module->addNotGate(NEW_ID, SigSpec(new_q, i), ff.sig_q[i]);
-						ff.val_init[i] = State::S0;
-					}
-					else
-					{
-						module->connect(ff.sig_q[i], SigSpec(new_q, i));
-						if (all_mode)
-							ff.val_init[i] = State::S0;
-					}
-
-				ff.sig_q = new_q;
-				ff.emit(module, name);
+				pool<int> bits;
+				for (int i = 0; i < ff.width; i++) {
+					if (ff.val_init.bits[i] == State::S1)
+						bits.insert(i);
+					else if (ff.val_init.bits[i] != State::S0 && all_mode)
+						ff.val_init.bits[i] = State::S0;
+				}
+				ff.flip_bits(bits);
+				ff.emit();
 			}
 		}
 	}