aboutsummaryrefslogtreecommitdiffstats
path: root/passes/techmap
diff options
context:
space:
mode:
Diffstat (limited to 'passes/techmap')
-rw-r--r--passes/techmap/abc.cc10
-rw-r--r--passes/techmap/dff2dffe.cc6
-rw-r--r--passes/techmap/extract.cc10
-rw-r--r--passes/techmap/muxcover.cc10
-rw-r--r--passes/techmap/techmap.cc20
5 files changed, 28 insertions, 28 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 7cb784505..9db8aafa7 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -333,12 +333,12 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp
{
std::string abc_sname = abc_name.substr(1);
bool isnew = false;
- if (abc_sname.substr(0, 4) == "new_")
+ if (abc_sname.compare(0, 4, "new_") == 0)
{
abc_sname.erase(0, 4);
isnew = true;
}
- if (abc_sname.substr(0, 5) == "ys__n")
+ if (abc_sname.compare(0, 5, "ys__n") == 0)
{
abc_sname.erase(0, 5);
if (std::isdigit(abc_sname.at(0)))
@@ -1562,10 +1562,10 @@ struct AbcPass : public Pass {
size_t pos = arg.find_first_of(':');
int lut_mode = 0, lut_mode2 = 0;
if (pos != string::npos) {
- lut_mode = std::atoi(arg.substr(0, pos).c_str());
- lut_mode2 = std::atoi(arg.substr(pos+1).c_str());
+ lut_mode = atoi(arg.substr(0, pos).c_str());
+ lut_mode2 = atoi(arg.substr(pos+1).c_str());
} else {
- lut_mode = std::atoi(arg.c_str());
+ lut_mode = atoi(arg.c_str());
lut_mode2 = lut_mode;
}
lut_costs.clear();
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 2dc577c73..c0bf3a665 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -377,7 +377,7 @@ struct Dff2dffePass : public Pass {
mod->remove(cell);
continue;
}
- if (cell->type.substr(0, 7) == "$_DFFE_") {
+ if (cell->type.begins_with("$_DFFE_")) {
if (min_ce_use >= 0) {
int ce_use = 0;
for (auto cell_other : mod->selected_cells()) {
@@ -390,8 +390,8 @@ struct Dff2dffePass : public Pass {
continue;
}
- bool clk_pol = cell->type.substr(7, 1) == "P";
- bool en_pol = cell->type.substr(8, 1) == "P";
+ bool clk_pol = cell->type.compare(7, 1, "P") == 0;
+ bool en_pol = cell->type.compare(8, 1, "P") == 0;
RTLIL::SigSpec tmp = mod->addWire(NEW_ID);
mod->addDff(NEW_ID, cell->getPort("\\C"), tmp, cell->getPort("\\Q"), clk_pol);
if (en_pol)
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index fff90f13c..e3b4faba1 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -54,7 +54,7 @@ public:
RTLIL::Const unified_param(RTLIL::IdString cell_type, RTLIL::IdString param, RTLIL::Const value)
{
- if (cell_type.substr(0, 1) != "$" || cell_type.substr(0, 2) == "$_")
+ if (!cell_type.begins_with("$") || cell_type.begins_with("$_"))
return value;
#define param_bool(_n) if (param == _n) return value.as_bool();
@@ -203,7 +203,7 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
continue;
std::string type = cell->type.str();
- if (sel == NULL && type.substr(0, 2) == "\\$")
+ if (sel == NULL && type.compare(0, 2, "\\$") == 0)
type = type.substr(1);
graph.createNode(cell->name.str(), type, (void*)cell);
@@ -594,7 +594,7 @@ struct ExtractPass : public Pass {
map = new RTLIL::Design;
for (auto &filename : map_filenames)
{
- if (filename.substr(0, 1) == "%")
+ if (filename.compare(0, 1, "%") == 0)
{
if (!saved_designs.count(filename.substr(1))) {
delete map;
@@ -613,10 +613,10 @@ struct ExtractPass : public Pass {
delete map;
log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
}
- Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
+ Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog"));
f.close();
- if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") {
+ if (filename.size() <= 3 || filename.compare(filename.size()-3, std::string::npos, ".il") != 0) {
Pass::call(map, "proc");
Pass::call(map, "opt_clean");
}
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index 45987392e..81546249c 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -675,11 +675,11 @@ struct MuxcoverPass : public Pass {
for (argidx = 1; argidx < args.size(); argidx++)
{
const auto &arg = args[argidx];
- if (arg.size() >= 6 && arg.substr(0,6) == "-mux2=") {
+ if (arg.size() >= 6 && arg.compare(0,6,"-mux2=") == 0) {
cost_mux2 = atoi(arg.substr(6).c_str());
continue;
}
- if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") {
+ if (arg.size() >= 5 && arg.compare(0,5,"-mux4") == 0) {
use_mux4 = true;
if (arg.size() > 5) {
if (arg[5] != '=') break;
@@ -687,7 +687,7 @@ struct MuxcoverPass : public Pass {
}
continue;
}
- if (arg.size() >= 5 && arg.substr(0,5) == "-mux8") {
+ if (arg.size() >= 5 && arg.compare(0,5,"-mux8") == 0) {
use_mux8 = true;
if (arg.size() > 5) {
if (arg[5] != '=') break;
@@ -695,7 +695,7 @@ struct MuxcoverPass : public Pass {
}
continue;
}
- if (arg.size() >= 6 && arg.substr(0,6) == "-mux16") {
+ if (arg.size() >= 6 && arg.compare(0,6,"-mux16") == 0) {
use_mux16 = true;
if (arg.size() > 6) {
if (arg[6] != '=') break;
@@ -703,7 +703,7 @@ struct MuxcoverPass : public Pass {
}
continue;
}
- if (arg.size() >= 6 && arg.substr(0,6) == "-dmux=") {
+ if (arg.size() >= 6 && arg.compare(0,6,"-dmux=") == 0) {
cost_dmux = atoi(arg.substr(6).c_str());
continue;
}
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index ceb053825..2708b08ae 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -243,7 +243,7 @@ struct TechmapWorker
if (positional_ports.count(portname) > 0)
portname = positional_ports.at(portname);
if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
- if (portname.substr(0, 1) == "$")
+ if (portname.begins_with("$"))
log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
continue;
}
@@ -341,7 +341,7 @@ struct TechmapWorker
RTLIL::Cell *c = module->addCell(c_name, it.second);
design->select(module, c);
- if (!flatten_mode && c->type.substr(0, 2) == "\\$")
+ if (!flatten_mode && c->type.begins_with("\\$"))
c->type = c->type.substr(1);
for (auto &it2 : c->connections_) {
@@ -406,7 +406,7 @@ struct TechmapWorker
continue;
std::string cell_type = cell->type.str();
- if (in_recursion && cell_type.substr(0, 2) == "\\$")
+ if (in_recursion && cell->type.begins_with("\\$"))
cell_type = cell_type.substr(1);
if (celltypeMap.count(cell_type) == 0) {
@@ -468,7 +468,7 @@ struct TechmapWorker
std::string cell_type = cell->type.str();
- if (in_recursion && cell_type.substr(0, 2) == "\\$")
+ if (in_recursion && cell->type.begins_with("\\$"))
cell_type = cell_type.substr(1);
for (auto &tpl_name : celltypeMap.at(cell_type))
@@ -602,7 +602,7 @@ struct TechmapWorker
}
for (auto conn : cell->connections()) {
- if (conn.first.substr(0, 1) == "$")
+ if (conn.first.begins_with("$"))
continue;
if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
continue;
@@ -725,7 +725,7 @@ struct TechmapWorker
for (auto &it : twd)
{
- if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty())
+ if (it.first.compare(0, 12, "_TECHMAP_DO_") != 0 || it.second.empty())
continue;
auto &data = it.second.front();
@@ -874,7 +874,7 @@ struct TechmapWorker
tpl->cloneInto(m);
for (auto cell : m->cells()) {
- if (cell->type.substr(0, 2) == "\\$")
+ if (cell->type.begins_with("\\$"))
cell->type = cell->type.substr(1);
}
@@ -1113,7 +1113,7 @@ struct TechmapPass : public Pass {
Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
} else {
for (auto &fn : map_files)
- if (fn.substr(0, 1) == "%") {
+ if (fn.compare(0, 1, "%") == 0) {
if (!saved_designs.count(fn.substr(1))) {
delete map;
log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1);
@@ -1128,7 +1128,7 @@ struct TechmapPass : public Pass {
yosys_input_files.insert(fn);
if (f.fail())
log_cmd_error("Can't open map file `%s'\n", fn.c_str());
- Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
+ Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
}
}
@@ -1143,7 +1143,7 @@ struct TechmapPass : public Pass {
free(p);
} else {
string module_name = it.first.str();
- if (module_name.substr(0, 2) == "\\$")
+ if (it.first.begins_with("\\$"))
module_name = module_name.substr(1);
celltypeMap[module_name].insert(it.first);
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-03 14:57:46 +0000