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-rw-r--r--passes/memory/memory_bram.cc4
-rw-r--r--passes/opt/opt_lut.cc94
-rw-r--r--passes/techmap/abc.cc4
-rw-r--r--passes/techmap/abc9.cc171
-rw-r--r--passes/techmap/extract_fa.cc12
5 files changed, 179 insertions, 106 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index ddc56d9b5..aa8f94149 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -68,6 +68,10 @@ struct rules_t
if (groups != GetSize(transp)) log_error("Bram %s variant %d has %d groups but only %d entries in 'transp'.\n", log_id(name), variant, groups, GetSize(transp));
if (groups != GetSize(clocks)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clocks'.\n", log_id(name), variant, groups, GetSize(clocks));
if (groups != GetSize(clkpol)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clkpol'.\n", log_id(name), variant, groups, GetSize(clkpol));
+
+ int group = 0;
+ for (auto e : enable)
+ if (e > dbits) log_error("Bram %s variant %d group %d has %d enable bits but only %d dbits.\n", log_id(name), variant, group, e, dbits);
}
vector<portinfo_t> make_portinfos() const
diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 26855fd70..182f63d99 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -105,7 +105,7 @@ struct OptLutWorker
SigSpec lut_input = cell->getPort("\\A");
int lut_arity = 0;
- log("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, log_id(module), log_id(cell));
+ log_debug("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, log_id(module), log_id(cell));
luts.insert(cell);
// First, find all dedicated logic we're connected to. This results in an overapproximation
@@ -147,15 +147,15 @@ struct OptLutWorker
{
if (lut_width <= dlogic_conn.first)
{
- log(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic->type.c_str(), log_id(module), log_id(lut_dlogic));
- log(" LUT input A[%d] not present.\n", dlogic_conn.first);
+ log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic->type.c_str(), log_id(module), log_id(lut_dlogic));
+ log_debug(" LUT input A[%d] not present.\n", dlogic_conn.first);
legal = false;
break;
}
if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic->getPort(dlogic_conn.second)))
{
- log(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic->type.c_str(), log_id(module), log_id(lut_dlogic));
- log(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic->getPort(dlogic_conn.second)));
+ log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic->type.c_str(), log_id(module), log_id(lut_dlogic));
+ log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic->getPort(dlogic_conn.second)));
legal = false;
break;
}
@@ -163,7 +163,7 @@ struct OptLutWorker
if (legal)
{
- log(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic->type.c_str(), log_id(module), log_id(lut_dlogic));
+ log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic->type.c_str(), log_id(module), log_id(lut_dlogic));
lut_legal_dlogics.insert(lut_dlogic);
for (auto &dlogic_conn : dlogic_map)
lut_dlogic_inputs.insert(dlogic_conn.first);
@@ -179,7 +179,7 @@ struct OptLutWorker
lut_arity++;
}
- log(" Cell implements a %d-LUT.\n", lut_arity);
+ log_debug(" Cell implements a %d-LUT.\n", lut_arity);
luts_arity[cell] = lut_arity;
luts_dlogics[cell] = lut_legal_dlogics;
luts_dlogic_inputs[cell] = lut_dlogic_inputs;
@@ -239,28 +239,26 @@ struct OptLutWorker
if (const0_match || const1_match || input_match != -1)
{
- log("Found redundant cell %s.%s.\n", log_id(module), log_id(lut));
+ log_debug("Found redundant cell %s.%s.\n", log_id(module), log_id(lut));
SigBit value;
if (const0_match)
{
- log(" Cell evaluates constant 0.\n");
+ log_debug(" Cell evaluates constant 0.\n");
value = State::S0;
}
if (const1_match)
{
- log(" Cell evaluates constant 1.\n");
+ log_debug(" Cell evaluates constant 1.\n");
value = State::S1;
}
if (input_match != -1) {
- log(" Cell evaluates signal %s.\n", log_signal(lut_inputs[input_match]));
+ log_debug(" Cell evaluates signal %s.\n", log_signal(lut_inputs[input_match]));
value = lut_inputs[input_match];
}
if (lut_dlogic_inputs.size())
- {
- log(" Not eliminating cell (connected to dedicated logic).\n");
- }
+ log_debug(" Not eliminating cell (connected to dedicated logic).\n");
else
{
SigSpec lut_output = lut->getPort("\\Y");
@@ -323,11 +321,11 @@ struct OptLutWorker
int lutB_arity = luts_arity[lutB];
pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB];
- log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
+ log_debug("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
if (index.query_is_output(lutA->getPort("\\Y")))
{
- log(" Not combining LUTs (cascade connection feeds module output).\n");
+ log_debug(" Not combining LUTs (cascade connection feeds module output).\n");
continue;
}
@@ -353,67 +351,51 @@ struct OptLutWorker
int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
if (lutA_dlogic_inputs.size())
- log(" Cell A is a %d-LUT with %zu dedicated connections. ", lutA_arity, lutA_dlogic_inputs.size());
+ log_debug(" Cell A is a %d-LUT with %zu dedicated connections. ", lutA_arity, lutA_dlogic_inputs.size());
else
- log(" Cell A is a %d-LUT. ", lutA_arity);
+ log_debug(" Cell A is a %d-LUT. ", lutA_arity);
if (lutB_dlogic_inputs.size())
- log("Cell B is a %d-LUT with %zu dedicated connections.\n", lutB_arity, lutB_dlogic_inputs.size());
+ log_debug("Cell B is a %d-LUT with %zu dedicated connections.\n", lutB_arity, lutB_dlogic_inputs.size());
else
- log("Cell B is a %d-LUT.\n", lutB_arity);
- log(" Cells share %zu input(s) and can be merged into one %d-LUT.\n", common_inputs.size(), lutM_arity);
+ log_debug("Cell B is a %d-LUT.\n", lutB_arity);
+ log_debug(" Cells share %zu input(s) and can be merged into one %d-LUT.\n", common_inputs.size(), lutM_arity);
const int COMBINE_A = 1, COMBINE_B = 2, COMBINE_EITHER = COMBINE_A | COMBINE_B;
int combine_mask = 0;
if (lutM_arity > lutA_width)
- {
- log(" Not combining LUTs into cell A (combined LUT wider than cell A).\n");
- }
+ log_debug(" Not combining LUTs into cell A (combined LUT wider than cell A).\n");
else if (lutB_dlogic_inputs.size() > 0)
- {
- log(" Not combining LUTs into cell A (cell B is connected to dedicated logic).\n");
- }
+ log_debug(" Not combining LUTs into cell A (cell B is connected to dedicated logic).\n");
else if (lutB->get_bool_attribute("\\lut_keep"))
- {
- log(" Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
- }
+ log_debug(" Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
else
- {
combine_mask |= COMBINE_A;
- }
if (lutM_arity > lutB_width)
- {
- log(" Not combining LUTs into cell B (combined LUT wider than cell B).\n");
- }
+ log_debug(" Not combining LUTs into cell B (combined LUT wider than cell B).\n");
else if (lutA_dlogic_inputs.size() > 0)
- {
- log(" Not combining LUTs into cell B (cell A is connected to dedicated logic).\n");
- }
+ log_debug(" Not combining LUTs into cell B (cell A is connected to dedicated logic).\n");
else if (lutA->get_bool_attribute("\\lut_keep"))
- {
- log(" Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
- }
+ log_debug(" Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
else
- {
combine_mask |= COMBINE_B;
- }
int combine = combine_mask;
if (combine == COMBINE_EITHER)
{
- log(" Can combine into either cell.\n");
+ log_debug(" Can combine into either cell.\n");
if (lutA_arity == 1)
{
- log(" Cell A is a buffer or inverter, combining into cell B.\n");
+ log_debug(" Cell A is a buffer or inverter, combining into cell B.\n");
combine = COMBINE_B;
}
else if (lutB_arity == 1)
{
- log(" Cell B is a buffer or inverter, combining into cell A.\n");
+ log_debug(" Cell B is a buffer or inverter, combining into cell A.\n");
combine = COMBINE_A;
}
else
{
- log(" Arbitrarily combining into cell A.\n");
+ log_debug(" Arbitrarily combining into cell A.\n");
combine = COMBINE_A;
}
}
@@ -423,7 +405,7 @@ struct OptLutWorker
pool<int> lutM_dlogic_inputs;
if (combine == COMBINE_A)
{
- log(" Combining LUTs into cell A.\n");
+ log_debug(" Combining LUTs into cell A.\n");
lutM = lutA;
lutM_inputs = lutA_inputs;
lutM_dlogic_inputs = lutA_dlogic_inputs;
@@ -432,7 +414,7 @@ struct OptLutWorker
}
else if (combine == COMBINE_B)
{
- log(" Combining LUTs into cell B.\n");
+ log_debug(" Combining LUTs into cell B.\n");
lutM = lutB;
lutM_inputs = lutB_inputs;
lutM_dlogic_inputs = lutB_dlogic_inputs;
@@ -441,7 +423,7 @@ struct OptLutWorker
}
else
{
- log(" Cannot combine LUTs.\n");
+ log_debug(" Cannot combine LUTs.\n");
continue;
}
@@ -466,17 +448,17 @@ struct OptLutWorker
if (input_unused && lutR_unique.size())
{
SigBit new_input = lutR_unique.pop();
- log(" Connecting input %d as %s.\n", i, log_signal(new_input));
+ log_debug(" Connecting input %d as %s.\n", i, log_signal(new_input));
lutM_new_inputs.push_back(new_input);
}
else if (sigmap(lutM_input[i]) == lutA_output)
{
- log(" Disconnecting cascade input %d.\n", i);
+ log_debug(" Disconnecting cascade input %d.\n", i);
lutM_new_inputs.push_back(SigBit());
}
else
{
- log(" Leaving input %d as %s.\n", i, log_signal(lutM_input[i]));
+ log_debug(" Leaving input %d as %s.\n", i, log_signal(lutM_input[i]));
lutM_new_inputs.push_back(lutM_input[i]);
}
}
@@ -494,9 +476,9 @@ struct OptLutWorker
lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
}
- log(" Cell A truth table: %s.\n", lutA->getParam("\\LUT").as_string().c_str());
- log(" Cell B truth table: %s.\n", lutB->getParam("\\LUT").as_string().c_str());
- log(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str());
+ log_debug(" Cell A truth table: %s.\n", lutA->getParam("\\LUT").as_string().c_str());
+ log_debug(" Cell B truth table: %s.\n", lutB->getParam("\\LUT").as_string().c_str());
+ log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str());
lutM->setParam("\\LUT", lutM_new_table);
lutM->setPort("\\A", lutM_new_inputs);
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 15e79f9d1..65c7d1bb8 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1172,8 +1172,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
continue;
}
}
-
- cell_stats[RTLIL::unescape_id(c->type)]++;
+ else
+ cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\_const0_" || c->type == "\\_const1_") {
RTLIL::SigSig conn;
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 5f448e37a..658bb1225 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -24,12 +24,13 @@
#if 0
// Based on &flow3 - better QoR but more experimental
-#define ABC_COMMAND_LUT "&st; &ps -l; "/*"&sweep -v;"*/" &scorr; " \
- "&st; &if {W}; &save; &st; &syn2; &if {W}; &save; &load; "\
- "&st; &if -g -K 6; &dch -f; &if {W}; &save; &load; "\
- "&st; &if -g -K 6; &synch2; &if {W}; &save; &load"
+#define ABC_COMMAND_LUT "&st; &ps -l; &sweep -v; &scorr; " \
+ "&st; &if {W}; &save; &st; &syn2; &if {W} -v; &save; &load; "\
+ "&st; &if -g -K 6; &dch -f; &if {W} -v; &save; &load; "\
+ "&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
+ "&mfs; &ps -l"
#else
-#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps -l; &if {W} {D} -v; &mfs; &ps -l"
+#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l"
#endif
@@ -53,6 +54,7 @@
#endif
#include "frontends/aiger/aigerparse.h"
+#include "kernel/utils.h"
#ifdef YOSYS_LINK_ABC
extern "C" int Abc_RealMain(int argc, char *argv[]);
@@ -570,13 +572,23 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
boxes.emplace_back(cell);
}
+ dict<SigBit, pool<IdString>> bit_drivers, bit_users;
+ TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
+ dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
+ dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
+
std::map<std::string, int> cell_stats;
for (auto c : mapped_mod->cells())
{
+ toposort.node(c->name);
+
RTLIL::Cell *cell = nullptr;
if (c->type == "$_NOT_") {
- RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
- RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
+ RTLIL::SigBit a_bit = c->getPort("\\A");
+ RTLIL::SigBit y_bit = c->getPort("\\Y");
+ bit_users[a_bit].insert(c->name);
+ bit_drivers[y_bit].insert(c->name);
+
if (!a_bit.wire) {
c->setPort("\\Y", module->addWire(NEW_ID));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
@@ -584,11 +596,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1);
}
else if (!lut_costs.empty() || !lut_file.empty()) {
- RTLIL::Cell* driving_lut = nullptr;
+ RTLIL::Cell* driver_lut = nullptr;
// ABC can return NOT gates that drive POs
if (!a_bit.wire->port_input) {
// If it's not a NOT gate that that comes from a PI directly,
- // find the driving LUT and clone that to guarantee that we won't
+ // find the driver LUT and clone that to guarantee that we won't
// increase the max logic depth
// (TODO: Optimise by not cloning unless will increase depth)
RTLIL::IdString driver_name;
@@ -596,50 +608,38 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
else
driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
- driving_lut = mapped_mod->cell(driver_name);
+ driver_lut = mapped_mod->cell(driver_name);
}
- if (!driving_lut) {
- // If a driver couldn't be found (could be from PI,
- // or from a box) then implement using a LUT
- cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
- RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset),
- RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
- 1);
- }
- else {
- auto driver_a = driving_lut->getPort("\\A").chunks();
- for (auto &chunk : driver_a)
- chunk.wire = module->wires_[remap_name(chunk.wire->name)];
- RTLIL::Const driver_lut = driving_lut->getParam("\\LUT");
- for (auto &b : driver_lut.bits) {
- if (b == RTLIL::State::S0) b = RTLIL::State::S1;
- else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
- }
+ if (!driver_lut) {
+ // If a driver couldn't be found (could be from PI or box CI)
+ // then implement using a LUT
cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
- driver_a,
- RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
- driver_lut);
+ RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
+ RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
+ RTLIL::Const::from_string("01"));
+ bit2sinks[cell->getPort("\\A")].push_back(cell);
+ cell_stats["$lut"]++;
}
+ else
+ not2drivers[c] = driver_lut;
+ continue;
}
- else {
- cell = module->addCell(remap_name(c->name), "$_NOT_");
- cell->setPort("\\A", RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset));
- cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
- cell_stats[RTLIL::unescape_id(c->type)]++;
- }
+ else
+ log_abort();
if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
continue;
}
cell_stats[RTLIL::unescape_id(c->type)]++;
- RTLIL::Cell *existing_cell = nullptr;
+ RTLIL::Cell *existing_cell = nullptr;
if (c->type == "$lut") {
- if (GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
- SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
- SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
+ if (GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT") == RTLIL::Const::from_string("01")) {
+ SigSpec my_a = module->wires_.at(remap_name(c->getPort("\\A").as_wire()->name));
+ SigSpec my_y = module->wires_.at(remap_name(c->getPort("\\Y").as_wire()->name));
module->connect(my_y, my_a);
- if (markgroups) c->attributes["\\abcgroup"] = map_autoidx;
+ if (markgroups) c->attributes["\\abcgroup"] = map_autoidx;
+ log_abort();
continue;
}
cell = module->addCell(remap_name(c->name), c->type);
@@ -666,10 +666,20 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
continue;
//log_assert(c.width == 1);
if (c.wire)
- c.wire = module->wires_[remap_name(c.wire->name)];
+ c.wire = module->wires_.at(remap_name(c.wire->name));
newsig.append(c);
}
cell->setPort(conn.first, newsig);
+
+ if (cell->input(conn.first)) {
+ for (auto i : newsig)
+ bit2sinks[i].push_back(cell);
+ for (auto i : conn.second)
+ bit_users[i].insert(c->name);
+ }
+ if (cell->output(conn.first))
+ for (auto i : conn.second)
+ bit_drivers[i].insert(c->name);
}
}
@@ -681,14 +691,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
if (!conn.first.is_fully_const()) {
auto chunks = conn.first.chunks();
for (auto &c : chunks)
- c.wire = module->wires_[remap_name(c.wire->name)];
+ c.wire = module->wires_.at(remap_name(c.wire->name));
conn.first = std::move(chunks);
}
if (!conn.second.is_fully_const()) {
auto chunks = conn.second.chunks();
for (auto &c : chunks)
if (c.wire)
- c.wire = module->wires_[remap_name(c.wire->name)];
+ c.wire = module->wires_.at(remap_name(c.wire->name));
conn.second = std::move(chunks);
}
module->connect(conn);
@@ -725,6 +735,79 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
}
+ for (auto &it : bit_users)
+ if (bit_drivers.count(it.first))
+ for (auto driver_cell : bit_drivers.at(it.first))
+ for (auto user_cell : it.second)
+ toposort.edge(driver_cell, user_cell);
+ bool no_loops = toposort.sort();
+ log_assert(no_loops);
+
+ for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
+ RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
+ log_assert(not_cell);
+ if (not_cell->type != "$_NOT_")
+ continue;
+ auto it = not2drivers.find(not_cell);
+ if (it == not2drivers.end())
+ continue;
+ RTLIL::Cell *driver_lut = it->second;
+ RTLIL::SigBit a_bit = not_cell->getPort("\\A");
+ RTLIL::SigBit y_bit = not_cell->getPort("\\Y");
+ RTLIL::Const driver_mask;
+
+ a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
+ y_bit.wire = module->wires_.at(remap_name(y_bit.wire->name));
+
+ auto jt = bit2sinks.find(a_bit);
+ if (jt == bit2sinks.end())
+ goto clone_lut;
+
+ for (auto sink_cell : jt->second)
+ if (sink_cell->type != "$lut")
+ goto clone_lut;
+
+ // Push downstream LUTs past inverter
+ for (auto sink_cell : jt->second) {
+ SigSpec A = sink_cell->getPort("\\A");
+ RTLIL::Const mask = sink_cell->getParam("\\LUT");
+ int index = 0;
+ for (; index < GetSize(A); index++)
+ if (A[index] == a_bit)
+ break;
+ log_assert(index < GetSize(A));
+ int i = 0;
+ while (i < GetSize(mask)) {
+ for (int j = 0; j < (1 << index); j++)
+ std::swap(mask[i+j], mask[i+j+(1 << index)]);
+ i += 1 << (index+1);
+ }
+ A[index] = y_bit;
+ sink_cell->setPort("\\A", A);
+ sink_cell->setParam("\\LUT", mask);
+ }
+
+ // Since we have rewritten all sinks (which we know
+ // to be only LUTs) to be after the inverter, we can
+ // go ahead and clone the LUT with the expectation
+ // that the original driving LUT will become dangling
+ // and get cleaned away
+clone_lut:
+ driver_mask = driver_lut->getParam("\\LUT");
+ for (auto &b : driver_mask.bits) {
+ if (b == RTLIL::State::S0) b = RTLIL::State::S1;
+ else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
+ }
+ auto cell = module->addLut(NEW_ID,
+ driver_lut->getPort("\\A"),
+ y_bit,
+ driver_mask);
+ for (auto &bit : cell->connections_.at("\\A")) {
+ bit.wire = module->wires_.at(remap_name(bit.wire->name));
+ bit2sinks[bit].push_back(cell);
+ }
+ }
+
//log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
log("ABC RESULTS: input signals: %8d\n", in_wires);
log("ABC RESULTS: output signals: %8d\n", out_wires);
diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc
index 9e6dc0d24..591bc43dd 100644
--- a/passes/techmap/extract_fa.cc
+++ b/passes/techmap/extract_fa.cc
@@ -174,8 +174,10 @@ struct ExtractFaWorker
SigSpec sig = root;
- if (!ce.eval(sig))
- log_abort();
+ if (!ce.eval(sig)) {
+ ce.pop();
+ return;
+ }
if (sig == State::S1)
func |= 1 << i;
@@ -214,8 +216,10 @@ struct ExtractFaWorker
SigSpec sig = root;
- if (!ce.eval(sig))
- log_abort();
+ if (!ce.eval(sig)) {
+ ce.pop();
+ return;
+ }
if (sig == State::S1)
func |= 1 << i;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 11:44:51 +0000