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-rw-r--r--techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v28
-rw-r--r--techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v14
-rw-r--r--techlibs/altera_intel/lpm_functions.v66
-rw-r--r--techlibs/altera_intel/max10/cells_arith_max10.v18
-rw-r--r--techlibs/altera_intel/max10/cells_comb_max10.v32
-rw-r--r--techlibs/altera_intel/max10/cells_map_max10.v14
-rw-r--r--techlibs/altera_intel/synth_intel.cc2
7 files changed, 87 insertions, 87 deletions
diff --git a/techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v b/techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v
index c32984859..a65d0c991 100644
--- a/techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v
+++ b/techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v
@@ -16,7 +16,7 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
-
+
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
@@ -37,23 +37,23 @@ module cycloneiv_io_obuf (output o, input i, input oe);
assign oe = oe;
endmodule // fiftyfivenm_io_obuf
-/* Altera MAX10 4-input non-fracturable LUT Primitive */
+/* Altera MAX10 4-input non-fracturable LUT Primitive */
module cycloneiv_lcell_comb (output combout, cout,
input dataa, datab, datac, datad, cin);
/* Internal parameters which define the behaviour
of the LUT primitive.
lut_mask define the lut function, can be expressed in 16-digit bin or hex.
- sum_lutc_input define the type of LUT (combinational | arithmetic).
+ sum_lutc_input define the type of LUT (combinational | arithmetic).
dont_touch for retiming || carry options.
- lpm_type for WYSIWYG */
-
+ lpm_type for WYSIWYG */
+
parameter lut_mask = 16'hFFFF;
parameter dont_touch = "off";
parameter lpm_type = "cycloneiv_lcell_comb";
parameter sum_lutc_input = "datac";
-
-reg [1:0] lut_type;
+
+reg [1:0] lut_type;
reg cout_rt;
reg combout_rt;
wire dataa_w;
@@ -84,7 +84,7 @@ endfunction
initial begin
if (sum_lutc_input == "datac") lut_type = 0;
- else
+ else
if (sum_lutc_input == "cin") lut_type = 1;
else begin
$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
@@ -94,11 +94,11 @@ end
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
if (lut_type == 0) begin // logic function
- combout_rt = lut_data(lut_mask, dataa_w, datab_w,
+ combout_rt = lut_data(lut_mask, dataa_w, datab_w,
datac_w, datad_w);
end
else if (lut_type == 1) begin // arithmetic function
- combout_rt = lut_data(lut_mask, dataa_w, datab_w,
+ combout_rt = lut_data(lut_mask, dataa_w, datab_w,
cin_w, datad_w);
end
cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
@@ -111,17 +111,17 @@ endmodule // cycloneiv_lcell_comb
/* Altera Cyclone IV Flip-Flop Primitive */
// TODO: Implement advanced simulation functions
-module dffeas ( output q,
- input d, clk, clrn, prn, ena,
+module dffeas ( output q,
+ input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload );
-
+
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q;
always @(posedge clk)
q <= d;
-
+
endmodule
diff --git a/techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v b/techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v
index 9860647ae..e02332712 100644
--- a/techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v
+++ b/techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v
@@ -16,7 +16,7 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
-
+
// Flip-flop D
module \$_DFF_P_ (input D, input C, output Q);
parameter WYSIWYG="TRUE";
@@ -26,12 +26,12 @@ endmodule //
// Input buffer map
module \$__inpad (input I, output O);
cycloneiv_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
-endmodule
+endmodule
-// Output buffer map
+// Output buffer map
module \$__outpad (input I, output O);
cycloneiv_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
-endmodule
+endmodule
// LUT Map
/* 0 -> datac
@@ -41,14 +41,14 @@ module \$lut (A, Y);
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
- generate
+ generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
cycloneiv_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
end else
- if(WIDTH == 3) begin
+ if(WIDTH == 3) begin
cycloneiv_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
@@ -58,4 +58,4 @@ module \$lut (A, Y);
endgenerate
endmodule //
-
+
diff --git a/techlibs/altera_intel/lpm_functions.v b/techlibs/altera_intel/lpm_functions.v
index 20dbf4a02..b4d02dcb9 100644
--- a/techlibs/altera_intel/lpm_functions.v
+++ b/techlibs/altera_intel/lpm_functions.v
@@ -16,48 +16,48 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
-
+
// NOTE: This is still WIP.
(* techmap_celltype = "$altpll" *)
-module _80_altpll_altera ( input [1:0] inclk,
- input fbin,
- input pllena,
- input clkswitch,
- input areset,
- input pfdena,
- input clkena,
- input extclkena,
- input scanclk,
- input scanaclr,
- input scanclkena,
- input scanread,
- input scanwrite,
- input scandata,
- input phasecounterselect,
+module _80_altpll_altera ( input [1:0] inclk,
+ input fbin,
+ input pllena,
+ input clkswitch,
+ input areset,
+ input pfdena,
+ input clkena,
+ input extclkena,
+ input scanclk,
+ input scanaclr,
+ input scanclkena,
+ input scanread,
+ input scanwrite,
+ input scandata,
+ input phasecounterselect,
input phaseupdown,
input phasestep,
input configupdate,
inout fbmimicbidir,
-
- output [width_clock-1:0] clk,
- output [3:0] extclk,
- output [1:0] clkbad,
- output enable0,
- output enable1,
- output activeclock,
- output clkloss,
- output locked,
- output scandataout,
- output scandone,
- output sclkout0,
- output sclkout1,
+
+ output [width_clock-1:0] clk,
+ output [3:0] extclk,
+ output [1:0] clkbad,
+ output enable0,
+ output enable1,
+ output activeclock,
+ output clkloss,
+ output locked,
+ output scandataout,
+ output scandone,
+ output sclkout0,
+ output sclkout1,
output phasedone,
output vcooverrange,
output vcounderrange,
output fbout,
output fref,
output icdrclk );
-
+
parameter intended_device_family = "MAX 10";
parameter operation_mode = "NORMAL";
parameter pll_type = "AUTO";
@@ -123,7 +123,7 @@ module _80_altpll_altera ( input [1:0] inclk,
parameter clk2_phase_shift = "0";
parameter clk1_phase_shift = "0";
parameter clk0_phase_shift = "0";
-
+
parameter clk9_duty_cycle = 50;
parameter clk8_duty_cycle = 50;
parameter clk7_duty_cycle = 50;
@@ -166,7 +166,7 @@ module _80_altpll_altera ( input [1:0] inclk,
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter m_initial = 1;
- parameter m = 0;
+ parameter m = 0;
parameter n = 1;
parameter m2 = 1;
parameter n2 = 1;
@@ -316,4 +316,4 @@ module _80_altpll_altera ( input [1:0] inclk,
parameter port_scanclkena = "PORT_CONNECTIVITY";
parameter using_fbmimicbidir_port = "ON";
-endmodule \ No newline at end of file
+endmodule
diff --git a/techlibs/altera_intel/max10/cells_arith_max10.v b/techlibs/altera_intel/max10/cells_arith_max10.v
index 497f44d99..82572fb5d 100644
--- a/techlibs/altera_intel/max10/cells_arith_max10.v
+++ b/techlibs/altera_intel/max10/cells_arith_max10.v
@@ -26,7 +26,7 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter LUT = 0;
-
+
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
@@ -44,19 +44,19 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH-1:0] C = {CO, CI};
-
+
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
- fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("cin")) _TECHMAP_REPLACE_
- ( .dataa(AA),
- .datab(BB),
- .datac(C),
- .datad(1'b0),
- .cin(C[i]),
+ fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("cin")) _TECHMAP_REPLACE_
+ ( .dataa(AA),
+ .datab(BB),
+ .datac(C),
+ .datad(1'b0),
+ .cin(C[i]),
.cout(CO[i]),
.combout(Y[i]) );
end: slice
endgenerate
assign X = C;
endmodule
-
+
diff --git a/techlibs/altera_intel/max10/cells_comb_max10.v b/techlibs/altera_intel/max10/cells_comb_max10.v
index cbf0954aa..51adb72e2 100644
--- a/techlibs/altera_intel/max10/cells_comb_max10.v
+++ b/techlibs/altera_intel/max10/cells_comb_max10.v
@@ -16,7 +16,7 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
-
+
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
@@ -25,7 +25,7 @@ module GND (output G);
assign G = 1'b0;
endmodule // GND
-/* Altera MAX10 devices Input Buffer Primitive */
+/* Altera MAX10 devices Input Buffer Primitive */
module fiftyfivenm_io_ibuf (output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
@@ -37,23 +37,23 @@ module fiftyfivenm_io_obuf (output o, input i, input oe);
assign oe = oe;
endmodule // fiftyfivenm_io_obuf
-/* Altera MAX10 4-input non-fracturable LUT Primitive */
+/* Altera MAX10 4-input non-fracturable LUT Primitive */
module fiftyfivenm_lcell_comb (output combout, cout,
input dataa, datab, datac, datad, cin);
-
+
/* Internal parameters which define the behaviour
of the LUT primitive.
lut_mask define the lut function, can be expressed in 16-digit bin or hex.
- sum_lutc_input define the type of LUT (combinational | arithmetic).
+ sum_lutc_input define the type of LUT (combinational | arithmetic).
dont_touch for retiming || carry options.
- lpm_type for WYSIWYG */
-
+ lpm_type for WYSIWYG */
+
parameter lut_mask = 16'hFFFF;
parameter dont_touch = "off";
parameter lpm_type = "fiftyfivenm_lcell_comb";
parameter sum_lutc_input = "datac";
-
-reg [1:0] lut_type;
+
+reg [1:0] lut_type;
reg cout_rt;
reg combout_rt;
wire dataa_w;
@@ -84,7 +84,7 @@ endfunction
initial begin
if (sum_lutc_input == "datac") lut_type = 0;
- else
+ else
if (sum_lutc_input == "cin") lut_type = 1;
else begin
$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
@@ -94,11 +94,11 @@ end
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
if (lut_type == 0) begin // logic function
- combout_rt = lut_data(lut_mask, dataa_w, datab_w,
+ combout_rt = lut_data(lut_mask, dataa_w, datab_w,
datac_w, datad_w);
end
else if (lut_type == 1) begin // arithmetic function
- combout_rt = lut_data(lut_mask, dataa_w, datab_w,
+ combout_rt = lut_data(lut_mask, dataa_w, datab_w,
cin_w, datad_w);
end
cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
@@ -111,17 +111,17 @@ endmodule // fiftyfivenm_lcell_comb
/* Altera MAX10 D Flip-Flop Primitive */
// TODO: Implement advanced simulation functions
-module dffeas ( output q,
- input d, clk, clrn, prn, ena,
+module dffeas ( output q,
+ input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload );
-
+
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q;
always @(posedge clk)
q <= d;
-
+
endmodule
diff --git a/techlibs/altera_intel/max10/cells_map_max10.v b/techlibs/altera_intel/max10/cells_map_max10.v
index 9ae6871fa..ed63c521b 100644
--- a/techlibs/altera_intel/max10/cells_map_max10.v
+++ b/techlibs/altera_intel/max10/cells_map_max10.v
@@ -16,7 +16,7 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
-
+
// Flip-flop D
module \$_DFF_P_ (input D, input C, output Q);
parameter WYSIWYG="TRUE";
@@ -26,12 +26,12 @@ endmodule //
// Input buffer map
module \$__inpad (input I, output O);
fiftyfivenm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
-endmodule
+endmodule
-// Output buffer map
+// Output buffer map
module \$__outpad (input I, output O);
fiftyfivenm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
-endmodule
+endmodule
// LUT Map
/* 0 -> datac
@@ -41,14 +41,14 @@ module \$lut (A, Y);
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
- generate
+ generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
fiftyfivenm_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
end else
- if(WIDTH == 3) begin
+ if(WIDTH == 3) begin
fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
@@ -58,4 +58,4 @@ module \$lut (A, Y);
endgenerate
endmodule //
-
+
diff --git a/techlibs/altera_intel/synth_intel.cc b/techlibs/altera_intel/synth_intel.cc
index 9710f7a85..003059458 100644
--- a/techlibs/altera_intel/synth_intel.cc
+++ b/techlibs/altera_intel/synth_intel.cc
@@ -110,7 +110,7 @@ struct SynthIntelPass : public ScriptPass {
if (!design->full_selection())
log_cmd_error("This comannd only operates on fully selected designs!\n");
-
+
if (family_opt != "max10" && family_opt !="cycloneiv" )
log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-18 05:54:59 +0000