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-rw-r--r--techlibs/altera_intel/Makefile.inc10
-rw-r--r--techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v128
-rw-r--r--techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v61
-rw-r--r--techlibs/altera_intel/lpm_functions.v319
-rw-r--r--techlibs/altera_intel/max10/cells_arith_max10.v62
-rw-r--r--techlibs/altera_intel/max10/cells_comb_max10.v128
-rw-r--r--techlibs/altera_intel/max10/cells_map_max10.v61
-rw-r--r--techlibs/altera_intel/synth_intel.cc199
8 files changed, 0 insertions, 968 deletions
diff --git a/techlibs/altera_intel/Makefile.inc b/techlibs/altera_intel/Makefile.inc
deleted file mode 100644
index 56ee56e88..000000000
--- a/techlibs/altera_intel/Makefile.inc
+++ /dev/null
@@ -1,10 +0,0 @@
-
-OBJS += techlibs/altera_intel/synth_intel.o
-
-#$(eval $(call add_share_file,share/altera_intel,techlibs/altera_intel/lpm_functions.v))
-$(eval $(call add_share_file,share/altera_intel/max10,techlibs/altera_intel/max10/cells_comb_max10.v))
-$(eval $(call add_share_file,share/altera_intel/cycloneiv,techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v))
-$(eval $(call add_share_file,share/altera_intel/max10,techlibs/altera_intel/max10/cells_map_max10.v))
-$(eval $(call add_share_file,share/altera_intel/cycloneiv,techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v))
-#$(eval $(call add_share_file,share/altera_intel/max10,techlibs/altera_intel/max10/cells_arith_max10.v))
-
diff --git a/techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v b/techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v
deleted file mode 100644
index a65d0c991..000000000
--- a/techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-module VCC (output V);
- assign V = 1'b1;
-endmodule // VCC
-
-module GND (output G);
- assign G = 1'b0;
-endmodule // GND
-
-/* Altera Cyclone IV (GX) devices Input Buffer Primitive */
-module cycloneiv_io_ibuf (output o, input i, input ibar);
- assign ibar = ibar;
- assign o = i;
-endmodule // fiftyfivenm_io_ibuf
-
-/* Altera Cyclone IV (GX) devices Output Buffer Primitive */
-module cycloneiv_io_obuf (output o, input i, input oe);
- assign o = i;
- assign oe = oe;
-endmodule // fiftyfivenm_io_obuf
-
-/* Altera MAX10 4-input non-fracturable LUT Primitive */
-module cycloneiv_lcell_comb (output combout, cout,
- input dataa, datab, datac, datad, cin);
-
-/* Internal parameters which define the behaviour
- of the LUT primitive.
- lut_mask define the lut function, can be expressed in 16-digit bin or hex.
- sum_lutc_input define the type of LUT (combinational | arithmetic).
- dont_touch for retiming || carry options.
- lpm_type for WYSIWYG */
-
-parameter lut_mask = 16'hFFFF;
-parameter dont_touch = "off";
-parameter lpm_type = "cycloneiv_lcell_comb";
-parameter sum_lutc_input = "datac";
-
-reg [1:0] lut_type;
-reg cout_rt;
-reg combout_rt;
-wire dataa_w;
-wire datab_w;
-wire datac_w;
-wire datad_w;
-wire cin_w;
-
-assign dataa_w = dataa;
-assign datab_w = datab;
-assign datac_w = datac;
-assign datad_w = datad;
-
-function lut_data;
-input [15:0] mask;
-input dataa, datab, datac, datad;
-reg [7:0] s3;
-reg [3:0] s2;
-reg [1:0] s1;
- begin
- s3 = datad ? mask[15:8] : mask[7:0];
- s2 = datac ? s3[7:4] : s3[3:0];
- s1 = datab ? s2[3:2] : s2[1:0];
- lut_data = dataa ? s1[1] : s1[0];
- end
-
-endfunction
-
-initial begin
- if (sum_lutc_input == "datac") lut_type = 0;
- else
- if (sum_lutc_input == "cin") lut_type = 1;
- else begin
- $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
- $finish();
- end
-end
-
-always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
- if (lut_type == 0) begin // logic function
- combout_rt = lut_data(lut_mask, dataa_w, datab_w,
- datac_w, datad_w);
- end
- else if (lut_type == 1) begin // arithmetic function
- combout_rt = lut_data(lut_mask, dataa_w, datab_w,
- cin_w, datad_w);
- end
- cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
-end
-
-assign combout = combout_rt & 1'b1;
-assign cout = cout_rt & 1'b1;
-
-endmodule // cycloneiv_lcell_comb
-
-/* Altera Cyclone IV Flip-Flop Primitive */
-// TODO: Implement advanced simulation functions
-module dffeas ( output q,
- input d, clk, clrn, prn, ena,
- input asdata, aload, sclr, sload );
-
-parameter power_up="dontcare";
-parameter is_wysiwyg="false";
- reg q;
-
- always @(posedge clk)
- q <= d;
-
-endmodule
-
-
-
diff --git a/techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v b/techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v
deleted file mode 100644
index e02332712..000000000
--- a/techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// Flip-flop D
-module \$_DFF_P_ (input D, input C, output Q);
- parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule //
-
-// Input buffer map
-module \$__inpad (input I, output O);
- cycloneiv_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
-endmodule
-
-// Output buffer map
-module \$__outpad (input I, output O);
- cycloneiv_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
-endmodule
-
-// LUT Map
-/* 0 -> datac
- 1 -> cin */
-module \$lut (A, Y);
- parameter WIDTH = 0;
- parameter LUT = 0;
- input [WIDTH-1:0] A;
- output Y;
- generate
- if (WIDTH == 1) begin
- assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
- end else
- if (WIDTH == 2) begin
- cycloneiv_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
- end else
- if(WIDTH == 3) begin
- cycloneiv_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
- end else
- if(WIDTH == 4) begin
- cycloneiv_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
- end else
- wire _TECHMAP_FAIL_ = 1;
- endgenerate
-endmodule //
-
-
diff --git a/techlibs/altera_intel/lpm_functions.v b/techlibs/altera_intel/lpm_functions.v
deleted file mode 100644
index b4d02dcb9..000000000
--- a/techlibs/altera_intel/lpm_functions.v
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// NOTE: This is still WIP.
-(* techmap_celltype = "$altpll" *)
-module _80_altpll_altera ( input [1:0] inclk,
- input fbin,
- input pllena,
- input clkswitch,
- input areset,
- input pfdena,
- input clkena,
- input extclkena,
- input scanclk,
- input scanaclr,
- input scanclkena,
- input scanread,
- input scanwrite,
- input scandata,
- input phasecounterselect,
- input phaseupdown,
- input phasestep,
- input configupdate,
- inout fbmimicbidir,
-
- output [width_clock-1:0] clk,
- output [3:0] extclk,
- output [1:0] clkbad,
- output enable0,
- output enable1,
- output activeclock,
- output clkloss,
- output locked,
- output scandataout,
- output scandone,
- output sclkout0,
- output sclkout1,
- output phasedone,
- output vcooverrange,
- output vcounderrange,
- output fbout,
- output fref,
- output icdrclk );
-
- parameter intended_device_family = "MAX 10";
- parameter operation_mode = "NORMAL";
- parameter pll_type = "AUTO";
- parameter qualify_conf_done = "OFF";
- parameter compensate_clock = "CLK0";
- parameter scan_chain = "LONG";
- parameter primary_clock = "inclk0";
- parameter inclk0_input_frequency = 1000;
- parameter inclk1_input_frequency = 0;
- parameter gate_lock_signal = "NO";
- parameter gate_lock_counter = 0;
- parameter lock_high = 1;
- parameter lock_low = 0;
- parameter valid_lock_multiplier = 1;
- parameter invalid_lock_multiplier = 5;
- parameter switch_over_type = "AUTO";
- parameter switch_over_on_lossclk = "OFF" ;
- parameter switch_over_on_gated_lock = "OFF" ;
- parameter enable_switch_over_counter = "OFF";
- parameter switch_over_counter = 0;
- parameter feedback_source = "EXTCLK0" ;
- parameter bandwidth = 0;
- parameter bandwidth_type = "UNUSED";
- parameter lpm_hint = "UNUSED";
- parameter spread_frequency = 0;
- parameter down_spread = "0.0";
- parameter self_reset_on_gated_loss_lock = "OFF";
- parameter self_reset_on_loss_lock = "OFF";
- parameter lock_window_ui = "0.05";
- parameter width_clock = 6;
- parameter width_phasecounterselect = 4;
- parameter charge_pump_current_bits = 9999;
- parameter loop_filter_c_bits = 9999;
- parameter loop_filter_r_bits = 9999;
- parameter scan_chain_mif_file = "UNUSED";
- parameter clk9_multiply_by = 1;
- parameter clk8_multiply_by = 1;
- parameter clk7_multiply_by = 1;
- parameter clk6_multiply_by = 1;
- parameter clk5_multiply_by = 1;
- parameter clk4_multiply_by = 1;
- parameter clk3_multiply_by = 1;
- parameter clk2_multiply_by = 1;
- parameter clk1_multiply_by = 1;
- parameter clk0_multiply_by = 1;
- parameter clk9_divide_by = 1;
- parameter clk8_divide_by = 1;
- parameter clk7_divide_by = 1;
- parameter clk6_divide_by = 1;
- parameter clk5_divide_by = 1;
- parameter clk4_divide_by = 1;
- parameter clk3_divide_by = 1;
- parameter clk2_divide_by = 1;
- parameter clk1_divide_by = 1;
- parameter clk0_divide_by = 1;
- parameter clk9_phase_shift = "0";
- parameter clk8_phase_shift = "0";
- parameter clk7_phase_shift = "0";
- parameter clk6_phase_shift = "0";
- parameter clk5_phase_shift = "0";
- parameter clk4_phase_shift = "0";
- parameter clk3_phase_shift = "0";
- parameter clk2_phase_shift = "0";
- parameter clk1_phase_shift = "0";
- parameter clk0_phase_shift = "0";
-
- parameter clk9_duty_cycle = 50;
- parameter clk8_duty_cycle = 50;
- parameter clk7_duty_cycle = 50;
- parameter clk6_duty_cycle = 50;
- parameter clk5_duty_cycle = 50;
- parameter clk4_duty_cycle = 50;
- parameter clk3_duty_cycle = 50;
- parameter clk2_duty_cycle = 50;
- parameter clk1_duty_cycle = 50;
- parameter clk0_duty_cycle = 50;
-
- parameter clk9_use_even_counter_mode = "OFF";
- parameter clk8_use_even_counter_mode = "OFF";
- parameter clk7_use_even_counter_mode = "OFF";
- parameter clk6_use_even_counter_mode = "OFF";
- parameter clk5_use_even_counter_mode = "OFF";
- parameter clk4_use_even_counter_mode = "OFF";
- parameter clk3_use_even_counter_mode = "OFF";
- parameter clk2_use_even_counter_mode = "OFF";
- parameter clk1_use_even_counter_mode = "OFF";
- parameter clk0_use_even_counter_mode = "OFF";
- parameter clk9_use_even_counter_value = "OFF";
- parameter clk8_use_even_counter_value = "OFF";
- parameter clk7_use_even_counter_value = "OFF";
- parameter clk6_use_even_counter_value = "OFF";
- parameter clk5_use_even_counter_value = "OFF";
- parameter clk4_use_even_counter_value = "OFF";
- parameter clk3_use_even_counter_value = "OFF";
- parameter clk2_use_even_counter_value = "OFF";
- parameter clk1_use_even_counter_value = "OFF";
- parameter clk0_use_even_counter_value = "OFF";
-
- parameter clk2_output_frequency = 0;
- parameter clk1_output_frequency = 0;
- parameter clk0_output_frequency = 0;
-
- parameter vco_min = 0;
- parameter vco_max = 0;
- parameter vco_center = 0;
- parameter pfd_min = 0;
- parameter pfd_max = 0;
- parameter m_initial = 1;
- parameter m = 0;
- parameter n = 1;
- parameter m2 = 1;
- parameter n2 = 1;
- parameter ss = 0;
- parameter l0_high = 1;
- parameter l1_high = 1;
- parameter g0_high = 1;
- parameter g1_high = 1;
- parameter g2_high = 1;
- parameter g3_high = 1;
- parameter e0_high = 1;
- parameter e1_high = 1;
- parameter e2_high = 1;
- parameter e3_high = 1;
- parameter l0_low = 1;
- parameter l1_low = 1;
- parameter g0_low = 1;
- parameter g1_low = 1;
- parameter g2_low = 1;
- parameter g3_low = 1;
- parameter e0_low = 1;
- parameter e1_low = 1;
- parameter e2_low = 1;
- parameter e3_low = 1;
- parameter l0_initial = 1;
- parameter l1_initial = 1;
- parameter g0_initial = 1;
- parameter g1_initial = 1;
- parameter g2_initial = 1;
- parameter g3_initial = 1;
- parameter e0_initial = 1;
- parameter e1_initial = 1;
- parameter e2_initial = 1;
- parameter e3_initial = 1;
- parameter l0_mode = "bypass";
- parameter l1_mode = "bypass";
- parameter g0_mode = "bypass";
- parameter g1_mode = "bypass";
- parameter g2_mode = "bypass";
- parameter g3_mode = "bypass";
- parameter e0_mode = "bypass";
- parameter e1_mode = "bypass";
- parameter e2_mode = "bypass";
- parameter e3_mode = "bypass";
- parameter l0_ph = 0;
- parameter l1_ph = 0;
- parameter g0_ph = 0;
- parameter g1_ph = 0;
- parameter g2_ph = 0;
- parameter g3_ph = 0;
- parameter e0_ph = 0;
- parameter e1_ph = 0;
- parameter e2_ph = 0;
- parameter e3_ph = 0;
- parameter m_ph = 0;
- parameter l0_time_delay = 0;
- parameter l1_time_delay = 0;
- parameter g0_time_delay = 0;
- parameter g1_time_delay = 0;
- parameter g2_time_delay = 0;
- parameter g3_time_delay = 0;
- parameter e0_time_delay = 0;
- parameter e1_time_delay = 0;
- parameter e2_time_delay = 0;
- parameter e3_time_delay = 0;
- parameter m_time_delay = 0;
- parameter n_time_delay = 0;
- parameter extclk3_counter = "e3" ;
- parameter extclk2_counter = "e2" ;
- parameter extclk1_counter = "e1" ;
- parameter extclk0_counter = "e0" ;
- parameter clk9_counter = "c9" ;
- parameter clk8_counter = "c8" ;
- parameter clk7_counter = "c7" ;
- parameter clk6_counter = "c6" ;
- parameter clk5_counter = "l1" ;
- parameter clk4_counter = "l0" ;
- parameter clk3_counter = "g3" ;
- parameter clk2_counter = "g2" ;
- parameter clk1_counter = "g1" ;
- parameter clk0_counter = "g0" ;
- parameter enable0_counter = "l0";
- parameter enable1_counter = "l0";
- parameter charge_pump_current = 2;
- parameter loop_filter_r = "1.0";
- parameter loop_filter_c = 5;
- parameter vco_post_scale = 0;
- parameter vco_frequency_control = "AUTO";
- parameter vco_phase_shift_step = 0;
- parameter lpm_type = "altpll";
-
- parameter port_clkena0 = "PORT_CONNECTIVITY";
- parameter port_clkena1 = "PORT_CONNECTIVITY";
- parameter port_clkena2 = "PORT_CONNECTIVITY";
- parameter port_clkena3 = "PORT_CONNECTIVITY";
- parameter port_clkena4 = "PORT_CONNECTIVITY";
- parameter port_clkena5 = "PORT_CONNECTIVITY";
- parameter port_extclkena0 = "PORT_CONNECTIVITY";
- parameter port_extclkena1 = "PORT_CONNECTIVITY";
- parameter port_extclkena2 = "PORT_CONNECTIVITY";
- parameter port_extclkena3 = "PORT_CONNECTIVITY";
- parameter port_extclk0 = "PORT_CONNECTIVITY";
- parameter port_extclk1 = "PORT_CONNECTIVITY";
- parameter port_extclk2 = "PORT_CONNECTIVITY";
- parameter port_extclk3 = "PORT_CONNECTIVITY";
- parameter port_clk0 = "PORT_CONNECTIVITY";
- parameter port_clk1 = "PORT_CONNECTIVITY";
- parameter port_clk2 = "PORT_CONNECTIVITY";
- parameter port_clk3 = "PORT_CONNECTIVITY";
- parameter port_clk4 = "PORT_CONNECTIVITY";
- parameter port_clk5 = "PORT_CONNECTIVITY";
- parameter port_clk6 = "PORT_CONNECTIVITY";
- parameter port_clk7 = "PORT_CONNECTIVITY";
- parameter port_clk8 = "PORT_CONNECTIVITY";
- parameter port_clk9 = "PORT_CONNECTIVITY";
- parameter port_scandata = "PORT_CONNECTIVITY";
- parameter port_scandataout = "PORT_CONNECTIVITY";
- parameter port_scandone = "PORT_CONNECTIVITY";
- parameter port_sclkout1 = "PORT_CONNECTIVITY";
- parameter port_sclkout0 = "PORT_CONNECTIVITY";
- parameter port_clkbad0 = "PORT_CONNECTIVITY";
- parameter port_clkbad1 = "PORT_CONNECTIVITY";
- parameter port_activeclock = "PORT_CONNECTIVITY";
- parameter port_clkloss = "PORT_CONNECTIVITY";
- parameter port_inclk1 = "PORT_CONNECTIVITY";
- parameter port_inclk0 = "PORT_CONNECTIVITY";
- parameter port_fbin = "PORT_CONNECTIVITY";
- parameter port_fbout = "PORT_CONNECTIVITY";
- parameter port_pllena = "PORT_CONNECTIVITY";
- parameter port_clkswitch = "PORT_CONNECTIVITY";
- parameter port_areset = "PORT_CONNECTIVITY";
- parameter port_pfdena = "PORT_CONNECTIVITY";
- parameter port_scanclk = "PORT_CONNECTIVITY";
- parameter port_scanaclr = "PORT_CONNECTIVITY";
- parameter port_scanread = "PORT_CONNECTIVITY";
- parameter port_scanwrite = "PORT_CONNECTIVITY";
- parameter port_enable0 = "PORT_CONNECTIVITY";
- parameter port_enable1 = "PORT_CONNECTIVITY";
- parameter port_locked = "PORT_CONNECTIVITY";
- parameter port_configupdate = "PORT_CONNECTIVITY";
- parameter port_phasecounterselect = "PORT_CONNECTIVITY";
- parameter port_phasedone = "PORT_CONNECTIVITY";
- parameter port_phasestep = "PORT_CONNECTIVITY";
- parameter port_phaseupdown = "PORT_CONNECTIVITY";
- parameter port_vcooverrange = "PORT_CONNECTIVITY";
- parameter port_vcounderrange = "PORT_CONNECTIVITY";
- parameter port_scanclkena = "PORT_CONNECTIVITY";
- parameter using_fbmimicbidir_port = "ON";
-
-endmodule
diff --git a/techlibs/altera_intel/max10/cells_arith_max10.v b/techlibs/altera_intel/max10/cells_arith_max10.v
deleted file mode 100644
index 82572fb5d..000000000
--- a/techlibs/altera_intel/max10/cells_arith_max10.v
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// NOTE: This is still WIP.
-(* techmap_celltype = "$alu" *)
-module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
- parameter A_SIGNED = 0;
- parameter B_SIGNED = 0;
- parameter A_WIDTH = 1;
- parameter B_WIDTH = 1;
- parameter Y_WIDTH = 1;
- parameter LUT = 0;
-
- input [A_WIDTH-1:0] A;
- input [B_WIDTH-1:0] B;
- output [Y_WIDTH-1:0] X, Y;
-
- input CI, BI;
- output [Y_WIDTH-1:0] CO;
-
- wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
-
- wire tempcombout;
- wire [Y_WIDTH-1:0] A_buf, B_buf;
- \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
- \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-
- wire [Y_WIDTH-1:0] AA = A_buf;
- wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
- wire [Y_WIDTH-1:0] C = {CO, CI};
-
- genvar i;
- generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
- fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("cin")) _TECHMAP_REPLACE_
- ( .dataa(AA),
- .datab(BB),
- .datac(C),
- .datad(1'b0),
- .cin(C[i]),
- .cout(CO[i]),
- .combout(Y[i]) );
- end: slice
- endgenerate
- assign X = C;
-endmodule
-
diff --git a/techlibs/altera_intel/max10/cells_comb_max10.v b/techlibs/altera_intel/max10/cells_comb_max10.v
deleted file mode 100644
index 51adb72e2..000000000
--- a/techlibs/altera_intel/max10/cells_comb_max10.v
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-module VCC (output V);
- assign V = 1'b1;
-endmodule // VCC
-
-module GND (output G);
- assign G = 1'b0;
-endmodule // GND
-
-/* Altera MAX10 devices Input Buffer Primitive */
-module fiftyfivenm_io_ibuf (output o, input i, input ibar);
- assign ibar = ibar;
- assign o = i;
-endmodule // fiftyfivenm_io_ibuf
-
-/* Altera MAX10 devices Output Buffer Primitive */
-module fiftyfivenm_io_obuf (output o, input i, input oe);
- assign o = i;
- assign oe = oe;
-endmodule // fiftyfivenm_io_obuf
-
-/* Altera MAX10 4-input non-fracturable LUT Primitive */
-module fiftyfivenm_lcell_comb (output combout, cout,
- input dataa, datab, datac, datad, cin);
-
-/* Internal parameters which define the behaviour
- of the LUT primitive.
- lut_mask define the lut function, can be expressed in 16-digit bin or hex.
- sum_lutc_input define the type of LUT (combinational | arithmetic).
- dont_touch for retiming || carry options.
- lpm_type for WYSIWYG */
-
-parameter lut_mask = 16'hFFFF;
-parameter dont_touch = "off";
-parameter lpm_type = "fiftyfivenm_lcell_comb";
-parameter sum_lutc_input = "datac";
-
-reg [1:0] lut_type;
-reg cout_rt;
-reg combout_rt;
-wire dataa_w;
-wire datab_w;
-wire datac_w;
-wire datad_w;
-wire cin_w;
-
-assign dataa_w = dataa;
-assign datab_w = datab;
-assign datac_w = datac;
-assign datad_w = datad;
-
-function lut_data;
-input [15:0] mask;
-input dataa, datab, datac, datad;
-reg [7:0] s3;
-reg [3:0] s2;
-reg [1:0] s1;
- begin
- s3 = datad ? mask[15:8] : mask[7:0];
- s2 = datac ? s3[7:4] : s3[3:0];
- s1 = datab ? s2[3:2] : s2[1:0];
- lut_data = dataa ? s1[1] : s1[0];
- end
-
-endfunction
-
-initial begin
- if (sum_lutc_input == "datac") lut_type = 0;
- else
- if (sum_lutc_input == "cin") lut_type = 1;
- else begin
- $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
- $finish();
- end
-end
-
-always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
- if (lut_type == 0) begin // logic function
- combout_rt = lut_data(lut_mask, dataa_w, datab_w,
- datac_w, datad_w);
- end
- else if (lut_type == 1) begin // arithmetic function
- combout_rt = lut_data(lut_mask, dataa_w, datab_w,
- cin_w, datad_w);
- end
- cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
-end
-
-assign combout = combout_rt & 1'b1;
-assign cout = cout_rt & 1'b1;
-
-endmodule // fiftyfivenm_lcell_comb
-
-/* Altera MAX10 D Flip-Flop Primitive */
-// TODO: Implement advanced simulation functions
-module dffeas ( output q,
- input d, clk, clrn, prn, ena,
- input asdata, aload, sclr, sload );
-
-parameter power_up="dontcare";
-parameter is_wysiwyg="false";
- reg q;
-
- always @(posedge clk)
- q <= d;
-
-endmodule
-
-
-
diff --git a/techlibs/altera_intel/max10/cells_map_max10.v b/techlibs/altera_intel/max10/cells_map_max10.v
deleted file mode 100644
index ed63c521b..000000000
--- a/techlibs/altera_intel/max10/cells_map_max10.v
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// Flip-flop D
-module \$_DFF_P_ (input D, input C, output Q);
- parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule //
-
-// Input buffer map
-module \$__inpad (input I, output O);
- fiftyfivenm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
-endmodule
-
-// Output buffer map
-module \$__outpad (input I, output O);
- fiftyfivenm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
-endmodule
-
-// LUT Map
-/* 0 -> datac
- 1 -> cin */
-module \$lut (A, Y);
- parameter WIDTH = 0;
- parameter LUT = 0;
- input [WIDTH-1:0] A;
- output Y;
- generate
- if (WIDTH == 1) begin
- assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
- end else
- if (WIDTH == 2) begin
- fiftyfivenm_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
- end else
- if(WIDTH == 3) begin
- fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
- end else
- if(WIDTH == 4) begin
- fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
- end else
- wire _TECHMAP_FAIL_ = 1;
- endgenerate
-endmodule //
-
-
diff --git a/techlibs/altera_intel/synth_intel.cc b/techlibs/altera_intel/synth_intel.cc
deleted file mode 100644
index 003059458..000000000
--- a/techlibs/altera_intel/synth_intel.cc
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/register.h"
-#include "kernel/celltypes.h"
-#include "kernel/rtlil.h"
-#include "kernel/log.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-struct SynthIntelPass : public ScriptPass {
- SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { }
-
- virtual void help() YS_OVERRIDE
- {
- // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
- log("\n");
- log(" synth_intel [options]\n");
- log("\n");
- log("This command runs synthesis for Intel FPGAs. This work is still experimental.\n");
- log("\n");
- log(" -family < max10 | cycloneiv >\n");
- log(" generate the synthesis netlist for the specified family.\n");
- log(" MAX10 is the default target if not family argument specified \n");
- log("\n");
- log(" -top <module>\n");
- log(" use the specified module as top module (default='top')\n");
- log("\n");
- log(" -vout <file>\n");
- log(" write the design to the specified Verilog netlist file. writing of an\n");
- log(" output file is omitted if this parameter is not specified.\n");
- log("\n");
- log(" -run <from_label>:<to_label>\n");
- log(" only run the commands between the labels (see below). an empty\n");
- log(" from label is synonymous to 'begin', and empty to label is\n");
- log(" synonymous to the end of the command list.\n");
- log("\n");
- log(" -retime\n");
- log(" run 'abc' with -dff option\n");
- log("\n");
- log("\n");
- log("The following commands are executed by this synthesis command:\n");
- help_script();
- log("\n");
- }
-
- string top_opt, family_opt, vout_file;
- bool retime;
-
- virtual void clear_flags() YS_OVERRIDE
- {
- top_opt = "-auto-top";
- family_opt = "max10";
- vout_file = "";
- retime = false;
- }
-
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
- {
- string run_from, run_to;
- clear_flags();
-
- size_t argidx;
- for (argidx = 1; argidx < args.size(); argidx++)
- {
- if (args[argidx] == "-family" && argidx+1 < args.size()) {
- family_opt = args[++argidx];
- continue;
- }
- if (args[argidx] == "-top" && argidx+1 < args.size()) {
- top_opt = "-top " + args[++argidx];
- continue;
- }
- if (args[argidx] == "-vout" && argidx+1 < args.size()) {
- vout_file = args[++argidx];
- continue;
- }
- if (args[argidx] == "-run" && argidx+1 < args.size()) {
- size_t pos = args[argidx+1].find(':');
- if (pos == std::string::npos)
- break;
- run_from = args[++argidx].substr(0, pos);
- run_to = args[argidx].substr(pos+1);
- continue;
- }
- if (args[argidx] == "-retime") {
- retime = true;
- continue;
- }
- break;
- }
- extra_args(args, argidx, design);
-
- if (!design->full_selection())
- log_cmd_error("This comannd only operates on fully selected designs!\n");
-
- if (family_opt != "max10" && family_opt !="cycloneiv" )
- log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
-
- log_header(design, "Executing SYNTH_INTEL pass.\n");
- log_push();
-
- run_script(design, run_from, run_to);
-
- log_pop();
- }
-
- virtual void script() YS_OVERRIDE
- {
- if (check_label("begin"))
- {
- if(check_label("family") && family_opt=="max10")
- {
- run("read_verilog -lib +/altera_intel/max10/cells_comb_max10.v");
- run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
- }
- else
- {
- run("read_verilog -lib +/altera_intel/cycloneiv/cells_comb_cycloneiv.v");
- run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
- }
- }
-
- if (check_label("flatten"))
- {
- run("proc");
- run("flatten");
- run("tribuf -logic");
- run("deminout");
- }
-
- if (check_label("coarse"))
- {
- run("synth -run coarse");
- }
-
- if (check_label("fine"))
- {
- run("opt -fast -full");
- run("memory_map");
- run("opt -full");
- run("techmap -map +/techmap.v");
- run("opt -fast");
- run("clean -purge");
- run("setundef -undriven -zero");
- if (retime || help_mode)
- run("abc -dff", "(only if -retime)");
- }
-
- if (check_label("map_luts"))
- {
- run("abc -lut 4");
- run("clean");
- }
-
- if (check_label("map_cells"))
- {
- run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
- if(family_opt=="max10")
- run("techmap -map +/altera_intel/max10/cells_map_max10.v");
- else
- run("techmap -map +/altera_intel/cycloneiv/cells_map_cycloneiv.v");
- run("clean -purge");
- }
-
- if (check_label("check"))
- {
- run("hierarchy -check");
- run("stat");
- run("check -noinit");
- }
-
- if (check_label("vout"))
- {
- if (!vout_file.empty() || help_mode)
- run(stringf("write_verilog -nodec -attr2comment -defparam -nohex -renameprefix yosys_ %s",
- help_mode ? "<file-name>" : vout_file.c_str()));
- }
- }
-} SynthIntelPass;
-
-PRIVATE_NAMESPACE_END
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 07:31:19 +0000