1 files changed, 6 insertions, 0 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 9a820f71c..3b7d55c6e 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -132,6 +132,12 @@ output Y;
 assign Y = ~((A | B) & (C | D));
 endmodule
 
+module \$_TBUF_ (A, E, Y);
+input A, E;
+output Y;
+assign Y = E ? A : 1'bz;
+endmodule
+
 module  \$_SR_NN_ (S, R, Q);
 input S, R;
 output reg Q;