diff options
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/simlib.v | 57 |
1 files changed, 39 insertions, 18 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index f3d652f0e..8f354a63d 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -65,10 +65,10 @@ parameter Y_WIDTH = 0; output [Y_WIDTH-1:0] Y; generate - if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:A + if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:BLOCK1 assign Y[A_WIDTH-1:0] = A_BUF.val; assign Y[Y_WIDTH-1:A_WIDTH] = 0; - end else begin:B + end else begin:BLOCK2 assign Y = +A_BUF.val; end endgenerate @@ -715,16 +715,33 @@ generate \$lut #( .WIDTH(WIDTH-1), .LUT(LUT ) ) lut0 ( .I(I[WIDTH-2:0]), .O(lut0_out) ); \$lut #( .WIDTH(WIDTH-1), .LUT(LUT >> (2**(WIDTH-1))) ) lut1 ( .I(I[WIDTH-2:0]), .O(lut1_out) ); end + + if (WIDTH > 0) begin:lutlogic + always @* begin + casez ({I[WIDTH-1], lut0_out, lut1_out}) + 3'b?11: O = 1'b1; + 3'b?00: O = 1'b0; + 3'b0??: O = lut0_out; + 3'b1??: O = lut1_out; + default: O = 1'bx; + endcase + end + end endgenerate +endmodule + +// -------------------------------------------------------- + +module \$assert (A, EN); + +input A, EN; + always @* begin - casez ({I[WIDTH-1], lut0_out, lut1_out}) - 3'b?11: O = 1'b1; - 3'b?00: O = 1'b0; - 3'b0??: O = lut0_out; - 3'b1??: O = lut1_out; - default: O = 1'bx; - endcase + if (A !== 1'b1 && EN === 1'b1) begin + $display("Assertation failed!"); + $finish; + end end endmodule @@ -953,8 +970,10 @@ input [ABITS-1:0] ADDR; output [WIDTH-1:0] DATA; initial begin - $display("ERROR: Found non-simulatable instance of $memrd!"); - $finish; + if (MEMID != "") begin + $display("ERROR: Found non-simulatable instance of $memrd!"); + $finish; + end end endmodule @@ -975,8 +994,10 @@ input [ABITS-1:0] ADDR; input [WIDTH-1:0] DATA; initial begin - $display("ERROR: Found non-simulatable instance of $memwr!"); - $finish; + if (MEMID != "") begin + $display("ERROR: Found non-simulatable instance of $memwr!"); + $finish; + end end endmodule @@ -1008,7 +1029,7 @@ input [WR_PORTS*ABITS-1:0] WR_ADDR; input [WR_PORTS*WIDTH-1:0] WR_DATA; reg [WIDTH-1:0] data [SIZE-1:0]; -event update_async_rd; +reg update_async_rd; genvar i; generate @@ -1032,21 +1053,21 @@ generate always @(WR_ADDR or WR_DATA or WR_EN) begin if (WR_EN[i]) begin data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ]; - #1 -> update_async_rd; + update_async_rd <= 1; update_async_rd <= 0; end end end else - if (RD_CLK_POLARITY[i] == 1) begin:rd_posclk + if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk always @(posedge WR_CLK[i]) if (WR_EN[i]) begin data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ]; - #1 -> update_async_rd; + update_async_rd <= 1; update_async_rd <= 0; end end else begin:rd_negclk always @(negedge WR_CLK[i]) if (WR_EN[i]) begin data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ]; - #1 -> update_async_rd; + update_async_rd <= 1; update_async_rd <= 0; end end end |